Intel 80C188XL Manuals

Manuals and User Guides for Intel 80C188XL. We have 1 Intel 80C188XL manual available for free PDF download: User Manual

Intel 80C188XL User Manual

Intel 80C188XL User Manual (405 pages)

Intel Microprocessor User's Manual

Brand: Intel | Category: Computer Hardware | Size: 2.01 MB

Table of Contents

Table of Contents
4
Chapter 1 Introduction

21
- How to Use this Manual
  21
- Comparison of 80C186 Modular Core Family Products
  21
- Related Documents
  22
- Related Documents and Software
  22
- Electronic Support Systems
  23
- Technical Support
  25
- Product Literature
  26
- Training Classes
  26
Chapter 2 Overview of the 80C186 Family Architecture

28
- Architectural Overview
  30
  - Execution Unit
    31
- Simplified Functional Block Diagram of the 80C186 Family CPU
  31
  - Bus Interface Unit
    32
- Physical Address Generation
  32
  - General Registers
    33
  - Segment Registers
    34
- Implicit Use of General Registers
  34
  - Instruction Pointer
    35
  - Segment Registers
    35
  - Flags
    36
  - Memory Segmentation
    37
- Processor Status Word
  38
  - Logical Addresses
    39
- Segment Locations in Physical Memory
  39
- Currently Addressable Segments
  40
- Logical and Physical Address
  41
  - Dynamically Relocatable Code
    42
- Logical Address Sources
  42
- Dynamic Code Relocation
  43
  - 2.1.10 Stack Implementation
    44
  - 2.1.11 Reserved Memory and I/O Space
    44
- Stack Operation
  45
- Software Overview
  46
  - Instruction Set
    46
    
    Data Transfer Instructions
    47
    
    Arithmetic Instructions
    48
- Flag Storage Format
  48
  - Arithmetic Instructions
    49
  - Bit Manipulation Instructions
    50
- Arithmetic Interpretation of 8-Bit Numbers
  50
  - String Instructions
    51
  - Program Transfer Instructions
    52
- String Instruction Register and Flag Use
  52
- Program Transfer Instructions
  54
- Interpretation of Conditional Transfers
  55
  - Processor Control Instructions
    56
  - Addressing Modes
    56
    
    Register and Immediate Operand Addressing Modes
    56
    
    Memory Addressing Modes
    57
- Memory Address Computation
  58
- Direct Addressing
  59
- Register Indirect Addressing
  60
- Based Addressing
  60
- Accessing a Structure with Based Addressing
  61
- Indexed Addressing
  62
- Accessing an Array with Indexed Addressing
  62
- Based Index Addressing
  63
- Accessing a Stacked Array with Based Index Addressing
  64
  - I/O Port Addressing
    65
- String Operand
  65
  - Data Types Used in the 80C186 Modular Core Family
    66
- Supported Data Types
  66
- C186 Modular Core Family Supported Data Types
  67
- Interrupts and Exception Handling
  68
  - Interrupt/Exception Processing
    68
- Interrupt Control Unit
  68
- Interrupt Vector Table
  69
  - Non-Maskable Interrupts
    71
- Interrupt Sequence
  71
  - Maskable Interrupts
    72
  - Exceptions
    72
  - Software Interrupts
    74
  - Interrupt Latency
    74
  - Interrupt Response Time
    75
  - Interrupt and Exception Priority
    75
- Interrupt Response Factors
  75
- Simultaneous NMI and Exception
  76
- Simultaneous NMI and Single Step Interrupts
  77
- Simultaneous NMI, Single Step and Maskable Interrupt
  78
Chapter 3

82
- Multiplexed Address and Data Bus
  82
- Address and Data Bus Concepts
  82
  - Bit Data Bus
    82
- Physical Data Bus Models
  83
- Bit Data Bus Byte Transfers
  84
- Bit Data Bus Even Word Transfers
  85
  - Bit Data Bus
    86
- Bit Data Bus Odd Word Transfers
  86
- Memory and I/O Interfaces
  87
- Bit Data Bus Word Transfers
  87
  - Bit Bus Memory and I/O Requirements
    88
- Bus Cycle Operation
  88
- Typical Bus Cycle
  89
- T-State Relation to CLKOUT
  89
- BIU State Diagram
  90
  - Address/Status Phase
    91
- T-State and Bus Phases
  91
- Address/Status Phase Signal Relationships
  92
- Demultiplexing Address Information
  93
- Bus Cycle Types
  93
  - Data Phase
    94
  - Wait States
    94
- Data Phase Signal Relationships
  95
- Typical Bus Cycle with Wait States
  96
- ARDY and SRDY Pin Block Diagram
  96
- Generating a Normally Not-Ready Bus Signal
  97
- Generating a Normally Ready Bus Signal
  98
  - Idle States
    99
- Normally Not-Ready System Timing
  99
- Normally Ready System Timings
  100
  - Bus Cycles
    101
  - Read Bus Cycles
    101
- Read Bus Cycle Types
  101
- Read Cycle Critical Timing Parameters
  101
- Typical Read Bus Cycle
  102
- Refresh Bus Cycles
  103
  - Write Bus Cycles
    103
- Read-Only Device Interface
  103
- Typical Write Bus Cycle
  104
- Write Bus Cycle Types
  104
- Bit Bus Read/Write Device Interface
  105
- Interrupt Acknowledge Bus Cycle
  106
- Write Cycle Critical Timing Parameters
  106
  - Interrupt Acknowledge Bus Cycle
    107
  - System Design Considerations
    108
- Typical 82C59A Interface
  108
- HALT Bus Cycle
  109
- HALT Bus Cycle Pin States
  110
  - Temporarily Exiting the HALT Bus State
    111
- Returning to HALT after a HOLD/HLDA Bus Exchange
  111
- Returning to HALT after a Refresh Bus Cycle
  112
- Exiting HALT
  113
- Returning to HALT after a DMA Bus Cycle
  113
- System Design Alternatives
  114
- Exiting HALT
  114
  - Buffering the Data Bus
    115
- Buffered AD Bus System
  116
  - Synchronizing Software and Hardware Events
    117
- Qualifying den with Chip-Selects
  117
  - Using a Locked Bus
    118
  - Using the Queue Status Signals
    119
- Queue Status Signal Decoding
  119
- Multi-Master Bus System Designs
  120
  - Entering Bus HOLD
    120
- Queue Status Timing
  120
  - HOLD Bus Latency
    121
- Timing Sequence Entering HOLD
  121
- Signal Condition Entering HOLD
  121
  - Refresh Operation During a Bus HOLD
    122
- Refresh Request During HOLD
  123
- Exiting HOLD
  124
- Latching HLDA
  124
- Bus Cycle Priorities
  125
- Exiting HOLD
  125
Chapter 4

130
- Peripheral Control Registers
  130
- Pcb Relocation Register
  130
- PCB Relocation Register
  131
- Peripheral Control Block
  132
- Reserved Locations
  133
- Accessing the Peripheral Control Block
  133
  - Bus Cycles
    133
  - READY Signals and Wait States
    133
  - F-Bus Operation
    134
    
    Writing the PCB Relocation Register
    135
    
    Accessing the Peripheral Control Registers
    135
    
    Accessing Reserved Locations
    135
- Setting the Pcb Base Location
  135
  - Considerations for the 80C187 Math Coprocessor Interface
    136
Chapter 5 Clock Generation

140
- Crystal Oscillator
  140
- Clock Generator
  140
  - Oscillator Operation
    141
- Ideal Operation of Pierce Oscillator
  141
- Crystal Connections to Microprocessor
  142
- Equations for Crystal Calculations
  143
  - Selecting Crystals
    144
  - Using an External Oscillator
    145
  - Output from the Clock Generator
    145
  - Reset and Clock Synchronization
    145
- Simple RC Circuit for Powerup Reset
  146
- Cold Reset Waveform
  147
- Warm Reset Waveform
  148
- Power Management
  149
- Clock Synchronization at Reset
  149
  - Power-Save Mode
    150
    
    Entering Power-Save Mode
    150
- Power-Save Register
  151
  - Leaving Power-Save Mode
    152
  - Example Power-Save Initialization Code
    152
- Power-Save Clock Transition
  152
  - Initializing the Power Management Unit for Power-Save Mode
    153
Chapter 6

156
- Common Methods for Generating Chip-Selects
  156
- Chip-Select Unit Features and Benefits
  156
- Chip-Select Unit Functional Overview
  157
- Common Chip-Select Generation Methods
  157
- Chip-Select Block Diagram
  158
- Chip-Select Relative Timings
  159
- UCS Reset Configuration
  160
- Programming
  161
  - Initialization Sequence
    161
- Chip-Select Unit Registers
  161
- UMCS Register Definition
  162
- LMCS Register Definition
  163
- MMCS Register Definition
  164
- PACS Register Definition
  165
- MPCS Register Definition
  166
  - Programming the Active Ranges
    167
    
    UCS Active Range
    167
- UCS Block Size and Starting Address
  167
- LCS Active Range
  168
- MCS Active Range
  168
- MCS3:0 Active Ranges
  169
- MCS Block Size and Start Address Restrictions
  169
- PCS Active Range
  170
  - Bus Wait State and Ready Control
    170
  - Overlapping Chip-Selects
    171
- Wait State and Ready Control Functions
  171
  - Memory or I/O Bus Cycle Decoding
    172
  - Programming Considerations
    172
- Chip-Selects and Bus Hold
  173
- Examples
  
  173
  - Example 1: Typical System Configuration
    173
  - Using Chip-Selects During HOLD
    173
  - Typical System
    174
    
    Initializing the Chip-Select Unit
    175
  - Refresh Control Unit Block Diagram
    180
Chapter 7

181
- The Role of the Refresh Control Unit
  181
- Refresh Control Unit Capabilities
  181
- Refresh Control Unit Operation
  181
- Refresh Control Unit Operation Flow Chart
  182
- Refresh Addresses
  183
- Refresh Address Formation
  183
- Guidelines for Designing Dram Controllers
  184
- Refresh Bus Cycles
  184
- Identification of Refresh Bus Cycles
  184
- Suggested DRAM Control Signal Timing Relationships
  185
- Programming the Refresh Control Unit
  186
  - Calculating the Refresh Interval
    186
  - Refresh Control Unit Registers
    186
- Formula for Calculating Refresh Interval for RFTIME Register
  186
- Refresh Base Address Register
  187
  - Refresh Clock Interval Register
    187
  - Refresh Control Register
    188
- Refresh Clock Interval Register
  188
  - Programming Example
    189
- Refresh Control Register
  189
  - Initializing the Refresh Control Unit
    190
- Refresh Operation and Bus Hold
  191
- Regaining Bus Control to Run a DRAM Refresh Bus Cycle
  192
- Functional Overview
  196
Chapter 8 Master Mode

197
- Generic Functions in Master Mode
  197
- Interrupt Control Unit in Master Mode
  197
  - Interrupt Masking
    198
  - Interrupt Priority
    198
- Default Interrupt Priorities
  198
  - Interrupt Nesting
    199
- Functional Operation in Master Mode
  200
  - Typical Interrupt Sequence
    200
  - Priority Resolution
    200
    
    Priority Resolution Example
    201
    
    Interrupts that Share a Single Source
    202
  - Cascading with External 8259As
    202
    
    Special Fully Nested Mode
    203
- Using External 8259A Modules in Cascade Mode
  203
  - Interrupt Acknowledge Sequence
    204
  - Polling
    204
- Fixed Interrupt Types
  204
  - Edge and Level Triggering
    205
  - Additional Latency and Response Time
    205
- Programming the Interrupt Control Unit
  206
- Interrupt Control Unit Latency and Response Time
  206
- Interrupt Control Unit Registers in Master Mode
  206
  - Interrupt Control Registers
    207
- Interrupt Control Register for Internal Sources
  208
- Interrupt Control Register for Noncascadable External Pins
  209
- Interrupt Control Register for Cascadable Interrupt Pins
  210
- Interrupt Request Register
  211
- Interrupt Mask Register
  211
- Priority Mask Register
  212
  - Interrupt Mask Register
    212
  - In-Service Register
    213
  - Priority Mask Register
    213
  - Poll and Poll Status Registers
    214
- In-Service Register
  214
- Poll Register
  215
  - End-Of-Interrupt (EOI) Register
    216
- Poll Status Register
  216
- Interrupt Status Register
  217
- End-Of-Interrupt Register
  217
- Slave Mode
  218
- Interrupt Status Register
  218
- Interrupt Control Unit in Slave Mode
  219
  - Slave Mode Programming
    220
- Interrupt Sources in Slave Mode
  220
  - Interrupt Vector Register
    221
- Interrupt Control Unit Register Comparison
  221
- Slave Mode Fixed Interrupt Type Bits
  221
- End-Of-Interrupt Register
  222
- Interrupt Vector Register (Slave Mode Only)
  222
  - Other Registers
    223
- End-Of-Interrupt Register in Slave Mode
  223
- Request, Mask, and In-Service Registers
  223
- Interrupt Vectoring in Slave Mode
  224
- Initializing the Interrupt Control Unit for Master Mode
  225
- Interrupt Response Time in Slave Mode
  225
  - Initializing the Interrupt Control Unit for Master Mode
    226
Chapter 10 Functional Overview

230
- Timer/Counter Unit Block Diagram
  231
- Counter Element Multiplexing and Timer Input Synchronization
  232
- Timers 0 and 1 Flow Chart
  233
- Programming the Timer/Counter Unit
  235
- Timer/Counter Unit Output Modes
  235
- Timer 0 and Timer 1 Control Registers
  236
- Timer 2 Control Register
  238
- Timer Count Registers
  239
- Initialization Sequence
  240
- Timer Maxcount Compare Registers
  240
  - Clock Sources
    241
  - Counting Modes
    241
- Timer 0 and 1 Clock Sources
  241
  - Retriggering
    242
  - Pulsed and Variable Duty Cycle Output
    243
- Timer Retriggering
  243
  - Enabling/Disabling Counters
    244
- Txout Signal Timing
  244
  - Timer Interrupts
    245
  - Programming Considerations
    245
- Timing
  245
  - Input Setup and Hold Timings
    245
  - Synchronization and Maximum Frequency
    246
    
    Timer/Counter Unit Application Examples
    246
  - Real-Time Clock
    246
  - Square-Wave Generator
    246
  - Digital One-Shot
    246
  - Configuring a Real-Time Clock
    247
  - Configuring a Square-Wave Generator
    250
  - Configuring a Digital One-Shot
    251
  - The DMA Transfer
    256
Chapter 9

256
- Functional Overview
  256
- Typical DMA Transfer
  257
  - DMA Transfer Directions
    258
  - Byte and Word Transfers
    258
  - Source and Destination Pointers
    258
- DMA Request Minimum Response Time
  259
- Source-Synchronized Transfers
  260
- Destination-Synchronized Transfers
  261
- Two-Channel DMA Module
  264
- Examples of DMA Priority
  265
- DMA Source Pointer (High-Order Bits)
  266
- DMA Source Pointer (Low-Order Bits)
  267
- DMA Destination Pointer (High-Order Bits)
  268
- DMA Destination Pointer (Low-Order Bits)
  269
- DMA Control Register
  270
- Transfer Count Register
  274
  - Initializing the DMA Unit
    278
  - Timed DMA Transfers
    281
- C187 Data Transfer Instructions
  288
- C187 Arithmetic Instructions
  289
  - Transcendental Instructions
    290
- C187 Comparison Instructions
  290
- C187 Transcendental Instructions
  290
  - Constant Instructions
    291
  - Processor Control Instructions
    291
- C187 Constant Instructions
  291
- C187 Processor Control Instructions
  291
  - C187 Data Types
    292
- Microprocessor and Coprocessor Operation
  292
- C187-Supported Data Types
  293
- C186 Modular Core Family/80C187 System Configuration
  294
  - Clocking the 80C187
    295
  - Processor Bus Cycles Accessing the 80C187
    295
- C187 I/O Port Assignments
  295
  - System Design Tips
    296
- C187 Configuration with a Partially Buffered Bus
  297
  - Exception Trapping
    298
- Example Math Coprocessor Routines
  298
- C187 Exception Trapping Via Processor Interrupt Pin
  299
  - Initialization Sequence for 80C187 Math Coprocessor
    300
  - Floating Point Math Routine Using FSINCOS
    301
- Entering/Leaving Once Mode
  304

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