Status Register Access Instructions; Load/Store Instructions - Intel PXA255 User Manual

Table 11-9. Saturated Data Processing Instruction Timings
Mnemonic
QADD
QSUB
QDADD
QDSUB
11.2.6

Status Register Access Instructions

Table 11-10. Status Register Access Instruction Timings
Mnemonic
MRS
MSR
11.2.7

Load/Store Instructions

Table 11-11. Load and Store Instruction Timings
Mnemonic
LDR
LDRB
LDRBT
LDRD
LDRH
LDRSB
LDRSH
LDRT
PLD
STR
STRB
STRBT
STRD
STRH
STRT
Intel® XScale™ Microarchitecture User's Manual
Minimum Issue Latency
1
1
1
1
Minimum Issue Latency
1
2 (6 if updating mode bits)
Minimum Issue Latency
1
1
1
1 (+1 if Rd is R12)
1
1
1
1
1
1
1
1
2
1
1
Performance Considerations
Minimum Result Latency
2
2
2
2
Minimum Result Latency
2
1
Minimum Result Latency
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for Rd; 4 for Rd+1; 2 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
N/A
1 for writeback of base
1 for writeback of base
1 for writeback of base
1 for writeback of base
1 for writeback of base
1 for writeback of base
11-7