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Performance Considerations
Table 11-6. Multiply Instruction Timings (Sheet 2 of 2)
Mnemonic
UMLAL
UMULL
a.
If the next instruction needs to use the result of the multiply for a shift by immediate or as Rn in a QDADD or QDSUB, one
extra cycle of result latency is added to the number listed.
Table 11-7. Multiply Implicit Accumulate Instruction Timings
Mnemonic
MIA
MIAxy
MIAPH
Table 11-8. Implicit Accumulator Access Instruction Timings
Mnemonic
MAR
MRA
a.
If the next instruction needs to use the result of the MRA for a shift by immediate or as Rn in a QDADD or QDSUB, one extra
cycle of result latency is added to the number listed.
11.2.5
Saturated Arithmetic Instructions
h
11-6
Rs Value
S-Bit
(Early Termination)
Value
0
Rs[31:15] = 0x00000
1
0
Rs[31:27] = 0x00
1
0
all others
1
0
Rs[31:15] = 0x00000
1
0
Rs[31:27] = 0x00
1
0
all others
1
Rs Value (Early
Minimum Issue
Termination)
Rs[31:16] = 0x0000
or
Rs[31:16] = 0xFFFF
Rs[31:28] = 0x0
or
Rs[31:28] = 0xF
all others
N/A
N/A
Minimum Issue Latency
2
1
Minimum
Minimum Result
Issue Latency
Latency
2
RdLo = 2; RdHi = 3
3
3
2
RdLo = 3; RdHi = 4
4
4
2
RdLo = 4; RdHi = 5
5
5
1
RdLo = 2; RdHi = 3
3
3
1
RdLo = 3; RdHi = 4
4
4
1
RdLo = 4; RdHi = 5
5
5
Minimum Result
Latency
Latency
1
1
1
2
1
3
1
1
1
2
Minimum Result Latency
2
a
(RdLo = 2; RdHi = 3)
Intel® XScale™ Microarchitecture User's Manual
Minimum Resource
a
Latency (Throughput)
2
3
3
4
4
5
2
3
3
4
4
5
Minimum Resource
Latency
(Throughput)
1
2
3
1
2
Minimum Resource Latency
(Throughput)
2
2
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