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Memory Management
If a MMU abort is generated during an instruction or data TLB lock operation, the Fault Status
Register is updated to indicate a Lock Abort (see
the exception is reported as a data abort.
Example 3-2. Locking Entries into the Instruction TLB
; R1, R2 and R3 contain the virtual addresses to translate and lock into
; the instruction TLB.
; The value in R0 is ignored in the following instruction.
; Hardware guarantees that accesses to CP15 occur in program order
MCR P15,0,R0,C8,C5,0
MCR P15,0,R1,C10,C4,0
MCR P15,0,R2,C10,C4,0 ; Translate
MCR P15,0,R3,C10,C4,0
CPWAIT
; For a description of CPWAIT, see
;
Section 2.3.3, "Additions to CP15 Functionality" on page 2-10
; The MMU is guaranteed to be updated at this point; the next instruction will
; see the locked instruction TLB entries.
Note: If exceptions are allowed to occur in the middle of this routine, the TLB may end up caching a
translation that is about to be locked. For example, if R1 is the virtual address of an interrupt
service routine and that interrupt occurs immediately after the TLB has been invalidated, the lock
operation will be ignored when the interrupt service routine returns back to this code sequence.
Software should disable interrupts (FIQ or IRQ) in this case.
As a general rule, software should avoid locking in anything other than Supervisor mode.
The proper procedure for locking entries into the data TLB is shown in
3-6
Section 2.3.4.4, "Data Aborts" on page
; Invalidate the entire instruction TLB
; Translate virtual address (R1) and lock into
; instruction TLB
; virtual address (R2) and lock into instruction TLB
; Translate virtual address (R3) and lock into
; instruction TLB
Intel® XScale™ Microarchitecture User's Manual
2-12), and
Example 3-3 on page
3-7.
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