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10.7.5 Conditional Execution Using TXRXCTRL .........................................................10-14
10.8
Transmit Register (TX) ..................................................................................................10-15
10.9
Receive Register (RX) ...................................................................................................10-15
10.10 Debug JTAG Access .....................................................................................................10-16
10.10.1 SELDCSR JTAG Command .............................................................................10-16
10.10.2 SELDCSR JTAG Register ................................................................................10-17
10.10.2.1 DBG.HLD_RST .................................................................................10-18
10.10.2.2 DBG.BRK..........................................................................................10-18
10.10.2.3 DBG.DCSR .......................................................................................10-18
10.10.3 DBGTX JTAG Command..................................................................................10-19
10.10.4 DBGTX JTAG Register .....................................................................................10-19
10.10.5 DBGRX JTAG Command .................................................................................10-20
10.10.6 DBGRX JTAG Register ....................................................................................10-20
10.10.6.1 RX Write Logic ..................................................................................10-21
10.10.6.2 DBGRX Data Register ......................................................................10-21
10.10.6.3 DBG.RR ............................................................................................10-22
10.10.6.4 DBG.V...............................................................................................10-22
10.10.6.5 DBG.RX ............................................................................................10-22
10.10.6.6 DBG.D...............................................................................................10-23
10.10.6.7 DBG.FLUSH .....................................................................................10-23
10.10.7 Debug JTAG Data Register Reset Values........................................................10-23
10.11 Trace Buffer ...................................................................................................................10-23
10.11.1 Trace Buffer CP Registers ................................................................................10-23
10.11.1.1 Checkpoint Registers........................................................................10-24
10.11.1.2 Trace Buffer Register (TBREG) ........................................................10-25
10.11.2 Trace Buffer Usage...........................................................................................10-25
10.12 Trace Buffer Entries.......................................................................................................10-27
10.12.1 Message Byte ...................................................................................................10-27
10.12.1.1 Exception Message Byte ..................................................................10-28
10.12.1.2 Non-exception Message Byte ...........................................................10-28
10.12.1.3 Address Bytes...................................................................................10-29
10.13 Downloading Code into the Instruction Cache...............................................................10-30
10.13.1 LDIC JTAG Command ......................................................................................10-30
10.13.2 LDIC JTAG Data Register ................................................................................10-31
10.13.3 LDIC Cache Functions......................................................................................10-32
10.13.4 Loading IC During Reset ..................................................................................10-33
10.13.4.1 Loading IC During Cold Reset for Debug .........................................10-34
10.13.4.2 Loading IC During a Warm Reset for Debug ....................................10-36
10.13.5 Dynamically Loading IC After Reset .................................................................10-38
10.13.5.1 Dynamic Code Download Synchronization .......................................10-39
10.13.6 Mini Instruction Cache Overview ......................................................................10-40
10.14 Halt Mode Software Protocol .........................................................................................10-40
10.14.1 Starting a Debug Session .................................................................................10-40
10.14.1.1 Setting up Override Vector Tables....................................................10-41
10.14.1.2 Placing the Handler in Memory .........................................................10-41
10.14.2 Implementing a Debug Handler ........................................................................10-42
10.14.2.1 Debug Handler Entry ........................................................................10-42
10.14.2.2 Debug Handler Restrictions ..............................................................10-42
10.14.2.3 Dynamic Debug Handler ...................................................................10-43
10.14.2.4 High-Speed Download ......................................................................10-44
10.14.3 Ending a Debug Session ..................................................................................10-45
Intel® XScale™ Microarchitecture User's Manual
Contents
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