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Table A-1. Pipelines and Pipe stages
Pipe / Pipestage
Main Execution Pipeline
F1/F2
ID
RF
X1
X2
XWB
Memory Pipeline
D1/D2
DWB
MAC Pipeline
M1-M5
MWB (not shown)
A.2.1.3.
Out Of Order Completion
Sequential consistency of instruction execution relates to two aspects: first, to the order in which
the instructions are completed; and second, to the order in which memory is accessed due to load
and store instructions. The Intel® XScale™ core preserves a weak processor consistency because
instructions may complete out of order, provided that no data dependencies exist.
While instructions are issued in-order, the main execution pipeline, memory, and MAC pipelines
are not lock-stepped, and, therefore, have different execution times. This means that instructions
may finish out of program order. Short 'younger' instructions may be finished earlier than long
'older' ones. The term 'to finish' is used here to indicate that the operation has been completed and
the result has been written back to the register file.
A.2.1.4.
Register Dependencies
In certain situations, the pipeline may need to be stalled because of register dependencies between
instructions. A register dependency occurs when a previous MAC or load instruction is about to
modify a register value that has not been returned to the register file and the current instruction
needs access to the same register.
If no register dependencies exist, the pipeline will not be stalled. For example, if a load operation
has missed the data cache, subsequent instructions that do not depend on the load may complete
independently.
A.2.1.5.
Use of Bypassing
The Intel® XScale™ core pipeline makes extensive use of bypassing to minimize data hazards.
Bypassing allows results forwarding from multiple sources, eliminating the need to stall the
pipeline.
Intel® XScale™ Microarchitecture User's Manual
Description
Handles data processing instructions
Instruction Fetch
Instruction Decode
Register File / Operand Shifter
ALU Execute
State Execute
Write-back
Handles load/store instructions
Data Cache Access
Data cache writeback
Handles all multiply instructions
Multiplier stages
MAC write-back - may occur during M2-M5
Optimization Guide
Covered In
Section A.2.3
Section A.2.3
Section A.2.3
Section A.2.3
Section A.2.3
Section A.2.3
Section A.2.3
Section A.2.4
Section A.2.4
Section A.2.4
Section A.2.5
Section A.2.5
Section A.2.5
A-3
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