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Performance Considerations
Table 11-12. Load and Store Multiple Instruction Timings
Mnemonic
LDM
STM
a.
LDM issue latency is 7 + N if R15 is in the register list and 2 + N if it is not. STM issue latency is calculated as 2 + N. N is
the number of registers to load or store.
11.2.8
Semaphore Instructions
Table 11-13. Semaphore Instruction Timings
Mnemonic
SWP
SWPB
11.2.9
Coprocessor Instructions
Table 11-14. CP15 Register Access Instruction Timings
Mnemonic
MRC
MCR
Table 11-15. CP14 Register Access Instruction Timings
Mnemonic
MRC
MCR
LDC
STC
11.2.10
Miscellaneous Instruction Timing
Table 11-16. SWI Instruction Timings
Mnemonic
SWI
11-8
a
Minimum Issue Latency
3 - 23
3 - 18
Minimum Issue Latency
5
5
Minimum Issue Latency
4
2
Minimum Issue Latency
7
7
10
7
Minimum latency to first instruction of SWI exception handler
Intel® XScale™ Microarchitecture User's Manual
Minimum Result Latency
1-3 for load data; 1 for writeback of base
1 for writeback of base
Minimum Result Latency
5
5
Minimum Result Latency
4
N/A
Minimum Result Latency
7
N/A
N/A
N/A
6
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