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Summary of Contents for Intel INTEL PENTIUM P6000 - SPECIFICATION UPDATE 2010
- Page 1 Intel® Pentium® P6000 and U5000 Mobile Processor Series Specification Update June 2010 Revision 002 Document Number: 323874-002...
- Page 2 Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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Page 3: Table Of Contents
Contents Preface ........................5 Summary Tables of Changes..................7 Identification Information ..................15 Errata ........................17 Specification Changes....................45 Specification Clarifications ..................46 Documentation Changes ..................47 Specification Update... -
Page 4: Revision History
Revision History Revision Revision Description Date -001 • Initial release May 2010 -002 • Added P6000 sku information June 2010 § Specification Update... -
Page 5: Preface
Documentation changes for the Intel® 64 and IA-32 Architecture Software Developer's Manual Volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document, the Intel® 64 and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow the link http://developer.intel.com/... - Page 6 Preface Nomenclature Errata are design defects or errors. These may cause the Arrandale Processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.
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Page 7: Summary Tables Of Changes
Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: Specification Update... - Page 8 Mobile Intel® Celeron® processor on 0.13 micron process in Micro-FCPGA package Intel® Celeron® M processor Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel® processor A100 and A110 with 512-KB L2 cache Intel® Pentium® M processor Mobile Intel®...
- Page 9 Intel® Core™ i7-800 and i5-700 desktop processor series AAO = Intel® Xeon® Processor 3400 Series AAP = Intel® Core™ i7-900 Mobile Processor Extreme Edition Series, Intel® Core™ i7-800 and i7-700 Mobile Processor Series AAT = Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series (Arrandale) AAU = Intel®...
- Page 10 Summary Tables of Changes Errata (Sheet 1 of 4) Steppings Number Status ERRATA No Fix The Processor May Report a #TS Instead of a #GP Fault REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types No Fix May Use an Incorrect Data Size or Lead to Memory-Ordering Violations...
- Page 11 Summary Tables of Changes Errata (Sheet 2 of 4) Steppings Number Status ERRATA An Enabled Debug Breakpoint or Single Step Trap May Be BG21 Taken after MOV SS/POP SS Instruction If It Is Followed by No Fix an Instruction That Signals a Floating Point Exception IA32_MPERF Counter Stops Counting during On-Demand BG22 No Fix...
- Page 12 LBRs May Not be Initialized During Power-On Reset of the BG52 No Fix Processor LBR, BTM or BTS Records May Have Incorrect Branch From Information After an Enhanced Intel SpeedStep® BG53 No Fix Technology Transition, T-states, C1E, or Adaptive Thermal Throttling...
- Page 13 Summary Tables of Changes Errata (Sheet 4 of 4) Steppings Number Status ERRATA MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo BG63 No Fix Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations PCI Express* x16 Port Logs Bad TLP Correctable Error When...
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Page 14: Specification Changes
Summary Tables of Changes Specification Changes Number Specification Changes None for this revision of this specification update. Specification Clarifications Number Specification Clarifications None for this revision of this specification update. Documentation Changes Number Documentation Changes None for this revision of this specification update. §... -
Page 15: Identification Information
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. Intel® Pentium® P6000 and U5000 Mobile Processor Series can be identified by the following register contents:... - Page 16 2.6666, repeating 6, is reported as @2.67 in brand string. Core frequency of 2.5333, is reported as @2.53 in brand string.) Intel® GPMT is supported. GPMT frequency runs at 366 MHz. This part supports C1, C1E, C3 and Deep Power Down Technology (code name C6 state) This part supports C1, C1E and C3 §...
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Page 17: Errata
Under certain conditions as described in the Software Developers Manual section “Out- of-Order Stores For String Operations in Pentium® 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this... - Page 18 #GP fault may not match the non-canonical address that caused the fault. Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially- available software. Workaround:None identified.
- Page 19 Errata BG5. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed before the exception handler is entered. •...
- Page 20 Errata BG7. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64-KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4-GB limit while the processor is operating in 32-bit mode.
- Page 21 ENTER instructions. This erratum is not expected to occur in Ring 3. Faults are usually processed in Ring 0 and stack switch occurs when transferring to Ring 0. Intel has not observed this erratum on any commercially-available software. Workaround:None identified.
- Page 22 Errata BG12. General Protection Fault (#GP) for Instructions Greater Than 15 Bytes May Be Preempted Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a #GP is signaled when the instruction is decoded. Under some circumstances, the #GP fault may be preempted by another lower priority fault (e.g., Page Fault (#PF)).
- Page 23 Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled “Switching to Protected Mode” recommends the FAR JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially-available software.
- Page 24 If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially-available software.
- Page 25 Operating System to observe higher processor utilization than actual, which could lead the OS into raising the P-state. During Intel TM1 activation, the OS P- state request is irrelevant and while on-demand throttling is enabled, it is expected that the OS will not be changing the P-state.
- Page 26 Intel Thermal Monitor will result in an artificial ceiling on the maximum core P-state. The ceiling is based on the core frequency at the time of Intel Thermal Monitor disable. This condition will only correct itself once the processor reaches its TCC activation temperature again.
- Page 27 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially-available software.
- Page 28 Implication: EOI transactions and interrupts may be blocked when core Deep Power Down Technology (code name C6 state) is used during interrupt service routines. Intel has not observed this erratum with any commercially-available software.
- Page 29 Errata BG32. FREEZE_WHILE_SMM Does Not Prevent Event from Pending PEBS during SMM Problem: In general, a PEBS record should be generated on the first count of the event after the counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from counting during SMM (System Management Mode).
- Page 30 10B (All Including Self) or 11B (All Excluding Self). Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle the broadcast IPI. Intel has not observed this erratum with any commercially-available software.
- Page 31 The aliasing of memory regions, a condition necessary for this erratum to occur, ® is documented as being unsupported in the Intel 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
- Page 32 Errata BG42. Performance Monitor Counters May Count Incorrectly Problem: Under certain circumstances, a general purpose performance counter, IA32_PMC0-4 (C1H - C4H), may count at core frequency or not count at all instead of counting the programmed event. Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed event.
- Page 33 Errata BG44. Back to Back Uncorrected Machine Check Errors May Overwrite IA32_MC3_STATUS.MSCOD Problem: When back-to-back uncorrected machine check errors occur that would both be logged in the IA32_MC3_STATUS MSR (40CH), the IA32_MC3_STATUS.MSCOD (bits [31:16]) field may reflect the status of the most recent error and not the first error. The rest of the IA32_MC3_STATUS MSR contains the information from the first error.
- Page 34 PDPTE Problem: On processors supporting Intel 64 architecture, the PS bit (Page Size, Bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an entry is ignored and no page fault will occur due to its being set.
- Page 35 Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may be signaled before pending interrupts are serviced.
- Page 36 Implication: If Intel® Hyper-Threading Technology is disabled, the Performance Monitor events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence of loads blocked by stores than have actually occurred. If Intel Hyper-Threading Technology is enabled, the counts of loads blocked by stores may be unpredictable and they could be higher or lower than the correct count.
- Page 37 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially-available software.
- Page 38 An unexpected page fault (#PF) may occur for a page under the following conditions: Implication: Software may see an unexpected page fault that indicates that there is no translation for the page. Intel has not observed this erratum with any commercially-available software or system.
- Page 39 Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel Turbo Boost Technology processor capabilities may report erroneous results. Workaround:It is possible for the BIOS to contain a workaround for this erratum.
- Page 40 Implication: This erratum may cause unpredictable system behavior. Intel has not observed this erratum with any commercially-available software. Specification Update...
- Page 41 Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor reset. Intel has not observed this erratum with any commercially-available software. Specification Update...
- Page 42 FP load around a 4-Gbyte boundary in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software. Workaround:If the FP Data Operand Pointer is used in a 64-bit operating system which may run code accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses are wrapped around a 4-Gbyte boundary.
- Page 43 Implication: Due to this erratum, the processor may not meet the JEDEC DDR3 DRAM specification requirement that states: “CKE cannot be registered low twice within a tRFC(min) window”. Intel has not observed any functional failure due to this erratum. Workaround:None identified.
- Page 44 Implication: Due to this erratum, the count value for some uncore Performance Monitoring Events may be inaccurate. The degree of under or over counting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
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Page 45: Specification Changes
Specification Changes Specification Changes There are no new Specification Changes in this Specification Update revision. § Specification Update... -
Page 46: Specification Clarifications
Specification Clarifications Specification Clarifications There are no new Specification Clarifications in this Specification Update revision. § Specification Update... -
Page 47: Documentation Changes
Documentation Changes Documentation Changes There are no new Document Changes in this Specification Update revision. § Specification Update...
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