Table of Contents
Advertisement
Example 8-1. Configuring the Performance Monitor
; Configure PMNC for instruction cache efficiency
;
evtCount0 = 7, evtCount1 = 0, flag = 0x7 to clear outstanding overflows
;
inten = 0x7set all counters to trigger an interrupt on overflow
;
C = 1
;
P = 1
;
E = 1
MOV
R0,#0x7777
MCR
P14,0,R0,C0,c0,0
; Counting begins
Counter overflow can be dealt with in the IRQ interrupt service routine as shown below:
Example 8-2. Interrupt Handling
IRQ_INTERRUPT_SERVICE_ROUTINE:
; Assume that performance counting interrupts are the only IRQ in the system
MRC
P14,0,R1,C0,c0,0
BIC
R2,R1,#1
MCR
P14,0,R2,C0,c0,0
MRC
P14,0,R3,C1,c0,0
MRC
P14,0,R4,C2,c0,0
MRC
P14,0,R5,C3,c0,0
<process the results>
SUBS PC,R14,#4
As an example, assume the following values in CCNT, PMN0, PMN1 and PMNC:
Example 8-3. Computing the Results
; Assume CCNT overflowed
CCNT = 0x0000,0020 ;Overflowed and continued counting
Number of instructions executed = PMN0 = 0x6AAA,AAAA
Number of instruction cache miss requests = PMN1 = 0x0555,5555
Instruction Cache miss-rate = 100 * PMN1/PMN0 = 5%
CPI = (CCNT + 2^32)/Number of instructions executed = 2.4 cycles/instruction
In the contrived example above, the instruction cache had a miss-rate of 5% and CPI was 2.4.
Intel® XScale™ Microarchitecture User's Manual
reset CCNT register
reset PMN0 and PMN1 registers
enable counting
; write R0 to PMNC
; read the PMNC register
; clear the enable bit
; clear interrupt flag and disable counting
; read CCNT register
; read PMN0 register
; read PMN1 register
; return from interrupt
Performance Monitoring
8-9
Advertisement
Table of Contents
