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Minimum Issue Latency (without Branch Misprediction) to the minimum branch latency
penalty number from
•
Minimum Resource Latency
The minimum cycle distance from the issue clock of the current multiply instruction to the
issue clock of the next multiply instruction assuming the second multiply does not incur a data
dependency and is immediately available from the instruction cache or memory interface.
For the following code fragment, here is an example of computing latencies:
Example 11-1. Computing Latencies
UMLAL
ADD
SUB
MOV
Table 11-2
at the issue column, the UMLAL instruction starts to issue on cycle 0 and the next instruction,
ADD, issues on cycle 2, so the Issue Latency for UMLAL is two. From the code fragment, there is
a result dependency between the UMLAL instruction and the SUB instruction. In
UMLAL starts to issue at cycle 0 and the SUB issues at cycle 5. thus the Result Latency is five.
Table 11-2. Latency Example
Cycle
0
1
2
3
4
5
6
7
11.2.2
Branch Instruction Timings
Table 11-3. Branch Instruction Timings (Those predicted by the BTB)
Mnemonic
B
BL
Intel® XScale™ Microarchitecture User's Manual
Table
11-1.
r6,r8,r0,r1
r9,r10,r11
r2,r8,r9
r0,r1
shows how to calculate Issue Latency and Result Latency for each instruction. Looking
umlal (1st cycle)
umlal (2nd cycle)
add
sub (stalled)
sub (stalled)
sub
mov
--
Minimum Issue Latency when Correctly
Predicted by the BTB
1
1
Performance Considerations
Issue
--
umlal
umlal
umlal & add
umlal
umlal
sub
mov
Minimum Issue Latency with Branch
Misprediction
Table
11-2,
Executing
5
5
11-3
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