Table of Contents
Advertisement
A.3.2
Bit Field Manipulation
The Intel® XScale™ core shift and logical operations provide a useful way of manipulating bit
fields. Bit field operations can be optimized as follows:
;Set the bit number specified by r1 in register r0
mov
orr
;Clear the bit number specified by r1 in register r0
mov
bic
;Extract the bit-value of the bit number specified by r1 of the
;value in r0 storing the value in r0
mov
and
;Extract the higher order 8 bits of the value in r0 storing
;the result in r1
mov
A.3.3
Optimizing the Use of Immediate Values
The Intel® XScale™ core MOV or MVN instruction should be used when loading an immediate
(constant) value into a register. Please refer to the
of immediate values that can be used in a MOV or MVN instruction. It is also possible to generate
a whole set of constant values using a combination of MOV, MVN, ORR, BIC, and ADD
instructions. The LDR instruction has the potential of incurring a cache miss in addition to
polluting the data and instruction caches. The code samples below illustrate cases when a
combination of the above instructions can be used to set a register to a constant value:
;Set the value of r0 to 127
mov
;Set the value of r0 to 0xfffffefb.
mvn
;Set the value of r0 to 257
mov
orr
;Set the value of r0 to 0x51f
mov
orr
;Set the value of r0 to 0xf100ffff
mvn
bic
; Set the value of r0 to 0x12341234
mov
orr
add
Note that it is possible to load any 32-bit value into a register using a sequence of four instructions.
A.3.4
Optimizing Integer Multiply and Divide
Multiplication by an integer constant should be optimized to make use of the shift operation
whenever possible.
;Multiplication of R0 by 2
mov
;Multiplication of R0 by 2
add
Intel® XScale™ Microarchitecture User's Manual
r2, #1
r0, r0, r2, asl r1
r2, #1
r0, r0, r2, asl r1
r1, r0, asr r1
r0, r1, #1
r1, r0, lsr #24
r0, #127
r0, #260
r0, #1
r0, r0, #256
r0, #0x1f
r0, r0, #0x500
r0, #0xff, 16
r0, r0, #0xe, 8
r0, #0x8d, 30
r0, r0, #0x1, 20
r0, r0, r0, LSL #16 ; shifter delay of 1 cycle
n
r0, r0, LSL #n
n
+1
r0, r0, r0, LSL #n
ARM* Architecture Reference Manual
Optimization Guide
for the set
A-11
Advertisement
Table of Contents
