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The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters
of each edition in which the revision was applied.
Edition
2nd edition Deletion of indication "under development" for all target products
pin → AV
AV
REF
A/D converter operation enable voltage
= 2.7 to 5.5 V → AV
AV
REF
Change of 113-pin plastic FBGA package in 1.4 Pin Configuration (Top View)
Modification of Table 2-1 Pin I/O Circuit Types
Addition of description on program area in 3.1.2 (1) Internal high-speed RAM
and (2) Internal expansion RAM
Change of Figure 3-10 Data To Be Saved to Stack Memory and Figure 3-11
Data To Be Restored from Stack Memory
Modification of [Description example] in 3.4.4 Short direct addressing
Addition of [Illustration] in 3.4.7 Based addressing, 3.4.8 Based indexed
addressing, and 3.4.9 Stack addressing
Modification of description of port 1 and port 4 in Table 4-1 Port Functions
Modification of Figure 4-4 P10 to P17 Block Diagram
Addition of Caution in 4.2.3 Port 2
Modification of Note in Format of Figure 4-18 Port Mode Registers (PM0,
PM2 to PM4, PM7 to PM11)
Modification of setting and addition of Caution 2 in Format of Figure 4-21
Pin Function Switching Registers (PF8 to PF11)
Addition of description in 5.5.1 Main system clock operations
Modification of Figure 6-1 Block Diagram of 16-Bit Timer/Event Counter 0
Addition of Figure 6-11 Configuration of PPG Output and Figure 6-12 PPG
Output Operation Timing
Modification of 6.6 (4) Capture register data retention timing and addition
of (13) STOP mode and main system clock stop mode settings
Deletion of <1> in 6.6 (7) Conflicting operations in 1st edition
Modification of Figure 7-6 Format of Carrier Generator Output Control
Register B0
Addition of input frequency from TMIB0 pin in Table 7-7 Square-Wave
Output Range with 16-Bit Resolution
Addition of description in 8.3 (2) 8-bit timer compare register 5n
(CR5n: n = 0, 1)
Addition of [Setting] in 8.5.2 External event counter operation
Addition of description on frequencies in [Setting] in 8.5.3 Square-wave
output operation
Modification of description of [Setting] in 8.5.4 PWM output operation
502
APPENDIX D REVISION HISTORY
Major Revision from Previous Edition
pin
DD
= 2.2 to 5.5 V
DD
User's Manual U15798EJ2V0UD
(1/4)
Applied to:
Throughout
CHAPTER 1 OUTLINE
CHAPTER 2 PIN FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 16-BIT TIMER/
EVENT COUNTER 0
CHAPTER 7 8-BIT TIMERS
A0, B0
CHAPTER 8 8-BIT TIMER/
EVENT COUNTERS 50, 51
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