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The following table shows the revision history up to the previous editions. The "Applied to:" column indicates the
chapters of each edition in which the revision was applied.
Edition
• Deletion of the following product
2nd
µ PD703117GJ-xxx-UEN
edition
• Addition of the following products
µ PD703116GJ-xxx-UEN, 703116GJ(A)-xxx-UEN, 703116GJ(A1)-xxx-UEN,
70F3116GJ(A)-UEN, 70F3116GJ(A1)-UEN
• Change of status of the following product from "under development" to "developed"
µ PD70F3116GJ-UEN
• Clarification of bits defined as reserved words in the device file (names of bits whose
numbers are in angle brackets)
Addition of Table 1-1 Differences Between V850E/IA1 and V850E/IA2
Addition of Table 1-2 Differences Between V850E/IA1 and V850E/IA2 Register Setting
Values
Modification of description in 1.3 Applications
Modification of description in 1.4 Ordering Information
Modification of Caution in 1.5 Pin Configuration
Addition of 1.7 Differences Between Products
Modification of pin status of ASTB (PCT6) and HLDRQ (PCM3) pins in 2.2 Pin Status
Modification of description in 2.4 Types of Pin I/O Circuit and Connection of Unused Pins
Modification of I/O circuit type from 5-K to 5-AC in 2.5 Pin I/O Circuits
Modification of description in 3.4.5 (1) (a) Memory map
Modification of description in 3.4.5 (2) Internal RAM area
Addition of Note and modification of Caution in 3.4.5 (3) On-chip peripheral I/O area
Deletion of part of description in 3.4.7 (1) Program space
Modification of part of description in example of wrap-around application in 3.4.7 (2) Data
space
Modification of Figure 3-6 Recommended Memory Map
Modification of description in 3.4.8 Peripheral I/O registers
Modification of description in 3.4.9 Programmable peripheral I/O registers
Modification of bit name in 3.4.9 (1) Peripheral area selection control register (BPC)
Modification of description of programmable peripheral I/O register area in 3.4.9
Programmable peripheral I/O registers
Modification of description on bits that can be manipulated, modification of description in
table, and addition of Remark in 3.4.11 System wait control register (VSWC)
Modification and addition of description in 4.2.1 Pin status during internal ROM, internal
RAM, and peripheral I/O access
Addition of Note in 4.3 Memory Block Function
Addition of Caution in 4.3.1 (1) Chip area selection control registers 0, 1 (CSC0, CSC1)
APPENDIX E REVISION HISTORY
Major Revision from Previous Edition
User's Manual U14492EJ3V0UD
(1/10)
Applied to:
Throughout
CHAPTER 1
INTRODUCTION
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
FUNCTION
CHAPTER 4 BUS
CONTROL
FUNCTION
823
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