Cautions Related To 16-Bit Timer/Event Counter 00 - NEC 78K0S/KB1+ User Manual
8-bit single-chip microcontrollers
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Also See for 78K0S/KB1+:
- Application note (49 pages) ,
- Application note (44 pages) ,
- Application note (38 pages)
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6.5
Cautions Related to 16-bit Timer/Event Counter 00
(1) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
(2) 16-bit timer counter 00 (TM00) operation
<1> 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop
<2> Even if TM00 is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010).
<R>
<3> When TM00 is read, count misses do not occur, since the input of the count clock is temporarily stopped
<4> If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to the
(3) Setting of 16-bit timer capture/compare registers 000, 010 (CR000, CR010)
<1> Set 16-bit timer capture/compare register 000 (CR000) to other than 0000H in the clear & start mode
<2> When the clear & start mode entered on a match between TM00 and CR000 is selected, CR000 should
<3> In the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR0n0 is
<4> If the new value of CR0n0 is less than the value of TM00, TM00 continues counting, overflows, and then
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-36. Start Timing of 16-bit Timer Counter 00 (TM00)
Count clock
0000H
TM00 count value
Timer start
mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the
operation.
and then resumed after the read.
TI000/TI010 pins.
entered on match between TM00 and CR000.
performed when this register is used as an external event counter.
not be specified as a capture register.
set to 0000H, an interrupt request (INTTM0n0) is generated when CR0n0 changes from 0000H to
0001H following overflow (FFFFH).
starts counting from 0 again. If the new value of CR0n0 is less than the old value, therefore, the timer
must be reset to be restarted after the value of CR0n0 is changed.
0001H
0002H
This means a 1-pulse count operation cannot be
User's Manual U17446EJ3V1UD
0003H
0004H
119
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