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STM32F038x6
2.3.6
Wakeup frame may not wakeup from STOP if t
HSI startup time
Description
Under specific conditions and if the START condition hold time t
to the HSI start-up time duration, the I
up the MCU from STOP.
To see the limitation, one of the conditions listed below has to be met:
1.
Timeout detection is enabled (TIMOUTEN=1 or TEXTEN=1) and the frame before the
wakeup frame is abnormally finished due to a I
2.
The slave arbitration is lost during the frame before the wakeup frame (ARLO=1).
3.
The MCU enters STOP mode while another slave is addressed, after the address
phase and before the STOP condition (BUSY=1).
4.
The MCU is in STOP mode and another slave is addressed before the I
addressed.
Note:
The last conditions 2, 3 and 4 can occur only in a multi-slave network.
In STOP mode, the HSI is switched on by the I
falling edge while SCL is high). The HSI is used to receive the address. HSI is switched off
after the address reception if received address is not the I
conditions above is met and if the SCL falling edge following the START condition occurs on
the first cycle of the I2CCLK clock (HSI), the address reception is not correctly done and the
address match wakeup interrupt is not generated.
Workaround
None at MCU level.
If the wakeup frame is not acknowledged by the I
duration of the START hold time: the master should decrease or increase the START
condition hold time for more than one HSI period and resend the wakeup frame.
2.3.7
Wrong behavior in Stop mode when wakeup from Stop mode is
disabled in I
Description
When wakeup from Stop mode is disabled in I
mode while a transfer is on going on the bus, some wrong behaviors may happen:
1.
BUSY flag can be wrongly set when the MCU exits Stop mode. This prevents from
initiating a transfer in master mode, as the START condition cannot be sent when
BUSY is set.
2.
If clock stretching is enabled (NOSTRETCH = 0), the I
low by the I
Stop mode is entered during the address phase of a transfer on the I
SCL = 0. Therefore the transfer may be stalled as long as the MCU is in Stop mode.
The probability of the occurrence depends also on the timings configuration, the
peripheral clock frequency and the I
These behaviors can occur in Slave mode and in Master mode in a multi-master topology.
2
C
2
C as long as the MCU is in Stop mode. This limitation may occur when the
DocID026423 Rev 2
Description of device limitations
2
C is not able to detect the address match and wake
2
C Timeout detection (TIMOUT=1).
2
C when a START condition is detected (SDA
2
C slave address. If one of the
2
C and if the master can program the
2
C (WUPEN = 0) and the MCU enters Stop
2
2
C bus frequency.
is close to
HD;STA
duration is very close
HD;STA
2
C is
C clock SCL may be stretched
2
C bus while
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