Fujitsu MB90335 Series Hardware Manual page 334

MB90335 Series
■ Range of Count at Pulse Width/cycle
Measurable ranges of pulse width/cycle vary depending on the selected combination of division ratios of
count clock and input divider.
Table 13.3-7 shows the measurement range list of machine clock when the clock frequency (called φ
hereafter) is 16 MHz.
Table 13.3-7 Pulse Width Measurement Range List
Divide ratio
None
4-frequency division
16-frequency division
64-frequency division
256-frequency division
Note: These values enclosed in brackets ( ) indicate the granularity per bit
■ Interrupt Request Generation
Two following interrupt requests can be generated in the pulse width measurement mode:
●
Interrupt request by overflow of timer
When an overflow is generated by the count up during the measurement, the overflow flag is set. When the
overflow interrupt request is permitted, an interrupt request occurs.
●
Interrupt request by measurement termination
When the measurement termination edge is detected, the measurement termination flag (EDIR) in the
PWCSR is set. If the measurement termination interrupt request is permitted, the interrupt request occurs.
The measurement termination flag (EDIR) is automatically cleared as soon as the measured result PWCR is
read.
CM44-10137-6E
in CKS1,CKS0=
DIV1 DIV0
00(φ/4)
0.17 μs to 10.92 ms
- -
(0.17 μs)
0.17 μs to 2.73 ms
0 0
(41.7 ns)
0.17 μs to 683 μs
0 1
(10.4 ns)
0.17 μs to 170 μs
1 0
(2.6 ns)
0.17 μs to 43 μs
1 1
(1.56 ns)
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 13 PWC TIMER
13.3 Movement of PWC Timer
in CKS1,CKS0=
01(φ/16)
0.17 μs to 43.7 ms
(0.67 μs)
0.17 μs to 10.92 ms
(0.17 μs)
0.17 μs to 2.73 ms
(41.7 ns)
0.17 μs to 683 μs
(10.4 ns)
0.17 μs to 171 μs
(6.25 ns)
in CKS1,CKS0=
10(φ/32)
0.17 μs to 87.4 ms
(1.33 μs)
0.17 μs to 21.85 ms
(0.67 μs)
0.17 μs to 5.46 ms
(0.17 μs)
0.17 μs to 1.36 ms
(41.7 ns)
0.17 μs to 341 μs
(12.5 ns)
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