Fujitsu MB90335 Series Hardware Manual page 120

MB90335 Series
3.8.3.4 DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL)
DMA buffer address pointer (DBAPH/DBAPM/DBAPL) sets the buffer address pointer.
The DBAPH/DBAPM/DBAPL can be set A23 to A00.
■ DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL)
The DMA buffer address pointer (DBAPH/DBAPM/DBAPL), a 24-bit register, contains the address used
for DMA transfer. DBAP are provided independently for the DMA channels to enable the DMA channels
to transfer data between any address of 16 Mbytes and I/O. If the BF bit (DBAP update/fix selection bit) of
the DMA control register (DMACS) is set to "updated", the 16 lower order bits (DBAPM, DBAPL) of the
DBAP will be incremented by 1 during byte transfer or by 2 during word transfer. The 8 high order bits
(DBAPH) will be unchanged in this case Figure 3.8-11 shows the DBAP configuration.
Figure 3.8-11 Bit Configuration of DMA Buffer address Pointer (DBAPH/DBAPM/DBAPL)
007922 , 007921
H
bit23
DBAPH/
DBAPM/
DBAPL
R/W : Readable/Writable
X : Undefined
Notes:
• In the DMA I/O register address pointer (DIOAH/DIOAL), the 000000
available for specification.
• In the DMA buffer address pointer (DBAPH/DBAPM/DBAPL), the 000000
available for specification.
μDMAC internal register DCSR, DSRH, DSRL, DSSR, DERH, or DERL, or an address of DMA
•
descriptor window register (DDWR) may not be specified in the DIOA or DBAP.
CM44-10137-6E
, 007920
H H
bit16 bit15
DBAPH DBAPM
R/W R/W
FUJITSU MICROELECTRONICS LIMITED
bit8 bit7 bit0
DBAPL
R/W
CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
Initial value
XXXXXX
H
to 00FFFF area is
H H
to FFFFFF area is
H H
99