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MB90335 Series
12.4.5
SOF Interruption FRAME Comparison Register (HFCOMP)
The SOF interrupt FRAME comparison register (HFCOMP) is a register used to set data
that is compared with the lower 8 bits of FRAME Number for SOF token. If the lower 8
bits of FRAME Number is compared with the HFCOMP register and a match is detected
with the SOFIRE bit in host control register 0 (HCNT0) set to "1", an interrupt will be
generated by setting the SOFIRQ bit in the host interrupt register (HIRQ) to "1" when
starting SOF transmission.
■ SOF Interruption FRAME Comparison Register (HFCOMP)
Figure 12.4-5 Bit Configuration of SOF Interruption FRAME Comparison Register (HFCOMP)
SOF interruption FRAME comparison register
bit
Address: 0000C5
H
→
Read/Write
→
Initial value
Reset On/Off at UDCC RST bit →
[bit 15 to bit 8] FRAMECOMP
It sets data that is to be compared with the lower 8 bits of Frame Number. It is not initialized with the
RST bit in the UDC control register (UDCC). To update them, you must set the RST bit in the UDC
control register (UDCC) to "0".
CM44-10137-6E
15
14
13
FUJITSU MICROELECTRONICS LIMITED
12
11
10
FRAMECOMP
(R/W)
(00000000
)
B
( )
CHAPTER 12 USB HOST
12.4 Register of USB HOST
9
8
HFCOMP
263
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