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MB90335 Series
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Timing transmission interrupt request generation
When sending interrupts are enabled (SSR0, SSR1: TIE=1) and if the sending data empty flag bit (SSR0,
SSR1: TDRE) is set to "1", a sending interrupt request is generated.
Note:
If the sending operation is set to be disabled (SCR0, SCR1: TXE=0, in the operation mode 1, also
including receiving operation disabled RXE) in the middle of sending operation, the sending data
empty flag bit is set (SSR0, SSR1: TDRE=1), the shift operation of the sending shift register is halted
and then UART communication operation is disabled. The send data written to the serial output data
register 1 before the transmission stops 0, 1 (SODR0, SODR1) is sent.
By default TDRE bit is "1". So, as soon as sending interrupts are enabled (TIE=1), the interrupt
indicating completion of transmission is generated. TDRE bit is a read-only bit and has no other way
to clear than by writing new data in the serial output data registers 0, 1 (SODR0, SODR1) to clear.
So be careful when to enable a sending interrupt.
CM44-10137-6E
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 18 UART
18.5 UART Interrupt
409
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