Fujitsu MB90335 Series Hardware Manual page 118

MB90335 Series
3.8.3.3 DMA Control Register (DMACS)
DMA control register (DMACS) controls the DMA transfer.
The following can be controlled by the DMACS.
• Direction control (IOA
• Transfer bit length (Byte and word)
• Address update (provided or not provided)
• Transfer interval
• Odd-numbered byte control at word transfer
■ DMA Control Register (DMACS)
The DMA control register (DMACS), an 8 bit length specifies update/fix, the transfer data format (byte or
word), the direction of transfer, and byte transfer, and issues a wait instruction of DMA buffer address
pointer and DMA I/O register address pointer. Figure 3.8-9 shows the DMACS configuration.
Figure 3.8-9 Bit Configuration of DMA Control Register (DMACS)
Address
007923
H
R/W: Readable/Writable
X : Undefined
CM44-10137-6E
→
BAP and BAP
bit7 bit6 bit5 bit4 bit3
RDY2 RDY1 IF BW
BYTEL
R/W R/W R/W R/W R/W
FUJITSU MICROELECTRONICS LIMITED
→
IOA)
bit2 bit1 bit0
Initial value
XXXXXXXX
BF DIR SE
R/W R/W R/W
SE
DMA transfer end control bit
0
It is not completed by request from peripheral function.
1
It is completed by request from peripheral function.
DIR Data transfer direction specification bit
0
DMA I/O register address pointer
1
DMA Buffer address pointer
BF
BAP update/fix selection bit
0
After data transfer, the buffer address pointer is updated.
1
After data transfer, the buffer address pointer is not updated.
Transfer data length specification bit
BW
0
Byte
1
Word
IF IOA update/fix selection bit
After data transfer, the I/O register address pointer is updated.
0
1 After data transfer, the I/O register address pointer is not updated.
BYTEL Byte transfer specification bit (only enabled for word transfer)
0
Even number of Bytes
1
Odd number of Bytes
RDY2 RDY1 Wait instruction bits (see Figure 8-10)
0 0 No wait is inserted between transfers.
0 1
A 1-cycle wait is inserted between transfers.
1 0 A 2-cycle wait is inserted between transfers.
A 3-cycle wait is inserted between transfers.
1 1
CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
B
DMA Buffer address pointer
DMA I/O register address pointer
97