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Bank Registers
Bank Registers (PCB, DTB, USB, SSB, ADB)
Bank Select Prefix
................................................ 40
Bank Select Prefix
BAP
Buffer Address Pointer (BAP)
Basic Component
The Serial On-Board Writing Basic Component
Baud Rate
Baud Rate of the External Clock (One-to-one Mode)
.......................................................... 413
Baud Rate of the External Clock Using the Dedicated Baud
Rate Generator
Baud Rate of the Internal Clock Using the Dedicated Baud
Rate Generator
UART Baud Rate Selection
Bidirectional Communication
Bidirectional Communication Function
Block Diagram
Block Diagram in Extended I/O Serial Interface
Block Diagram of 16-bit Reload Timer
Block Diagram of 8/16-bit PPG Timer
Block Diagram of Address Match Detection Function
.......................................................... 461
Block Diagram of Clock Generation Section
Block Diagram of Delayed Interrupt Generation Module
.......................................................... 109
Block Diagram of DTP/External Interrupt
Block Diagram of External Reset Pin
2
Block Diagram of I
C Interface
Block Diagram of Low-power Consumption Control Circuit
.......................................................... 139
Block Diagram of PWC Timer
Block Diagram of ROM Mirror Function Select Module
.......................................................... 456
Block Diagram of the MB90335 Series
Block Diagram of Time-base Timer
Block Diagram of UART
Block Diagram of USB Function
Block Diagram of Watchdog Timer
UART Block Diagram of USB HOST
Buffer Address Pointer
Buffer Address Pointer (BAP)
Bus Error
.......................................................... 448
Bus Error
Bus Mode
........................................................ 158
Bus Modes
Set Bit of Bus Mode (M1, M0)
C
Calculating
Calculating the Execution Cycle Count
Calculation
Calculation Method of Pulse Width/cycle
CCR
Condition Code Register (CCR)
Chip Erase
All Data Erase from Flash Memory (Chip Erase)
............ 37
................................. 78
......... 514
...................................... 412
...................................... 411
.................................. 410
.................... 422
......... 368
.................... 321
..................... 341
............. 126
................ 358
...................... 116
.............................. 433
............................... 291
........................ 7
........................ 172
...................................... 388
............................ 195
........................ 187
..................... 246
................................. 78
.............................. 160
.................... 555
................. 312
............................... 33
....... 505
Chip Erasure
..........................................505
Notes on Chip Erasure
CKSCR
Configuration of Clock Select Register (CKSCR)
Clock
Acquiring Transfer Speed of Destination USB Device and
Selecting Clock
Block Diagram of Clock Generation Section
...............................................125
Clock Supply Map
Connection of Oscillator and External Clock
Count Clock and Maximum Cycle
..................................303, 354
Count Clock Selection
Function of Clock Supply
...................................................131
Machine Clock
Oscillation Clock Frequency and Serial Clock Input
.............................................516
Frequency
..............................................124
Overview of Clock
Selection of PLL Clock Multiplication Rate
Clock Generation Section
Block Diagram of Clock Generation Section
Clock Mode
.......................................................137
Clock Mode
Event Count Mode (External Clock Mode)
External Shift Clock Mode
............................................319
Internal Clock Mode
Internal Clock Mode (Single Shot Mode)
Internal Shift Clock Mode
Operation of Internal Clock Mode (Reload Mode)
.........................................155
Switching Clock Mode
Transition of Clock Mode
Clock Select Register
Configuration of Clock Select Register (CKSCR)
Clock Supply Map
...............................................125
Clock Supply Map
CMR
Common Register Bank Prefix (CMR)
Command Issuance
Notes on Command Issuance
Command Sequence
Command Sequence Table
Common Register Bank Prefix
Common Register Bank Prefix (CMR)
Communication
Bidirectional Communication Function
Master/Slave Mode Communication Function
Communication Prescaler Control Register
Communication Prescaler Control Register (SDCR)
..........................................................375
Condition Code Register
Condition Code Register (CCR)
Connected Detection
Connected Detection of External USB Device
Connection Example
Connection Example in Single-chip Mode (when Using
..........................................519
User Power)
.......128
......................................271
..............126
.............133
...........................308
..............................171, 178
..............130
..............126
................319
....................................378
..................334
.....................................378
......331
.....................................130
.......128
.......................41
.................................492
....................................491
.......................41
....................422
............424
................................33
............271
599
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