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MB90335 Series
■ Block Diagram of I
Figure 19.1-1 shows the block diagram of I
CM44-10137-6E
2
C Interface
Figure 19.1-1 Block Diagram of I
ICCR0
2
I
C enable
EN
Clock divider 1
5
6
ICCR0
CS4
Clock selection 1
CS3
Clock divider 2
CS2
2 4 8 16 32 64 128
CS1
CS0
Clock selection 2
IBSR0
Bus busy
BB
Repeat start
RSC
Last Bit
Condition detection
LRB
Send/
receive
TRX
FBT
AL
Arbitration lost detection
IBCR0
BER
BEIE
Interrupt request
INTE
INT
IBCR0
Start
SCC
Master
MSS
ACK enable
Condition generation
ACK
GC-ACK enable
GCAA
IBSR0
Slave
AAS
Slave address
Global call
GCA
FUJITSU MICROELECTRONICS LIMITED
2
C interface.
2
C Interface
Peripheral clock
7
8
Sync
256
Shift clock
edge change
timing
Start
Stop
Error
First Byte
IRQ #17
End
Start
Stop
IDAR0
compare
IADR0
2
CHAPTER 19 I
C INTERFACE
2
19.1 I
C Interface Outline
Shift clock generation
SCL0
SDA0
433
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