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MB90335 Series
11.3.1
UDC Control Register (UDCC)
UDC control register (UDCC) controls the UDC core circuit.
■ UDC Control Register (UDCC)
Figure 11.3-3 shows the bit configuration of the UDC control register (UDCC).
Address
bit
7
0000D0
RST
H
1
R/W
Address
bit
15
0000D1
Reserved
H
0
-
R/W : Readable/Writable
Note:
The UDC control register(UDCC) should be set when bit7:RST=1 and not be rewritten when USB is
in operating. However, bit 6 of RESUM and bit 4 of USTP are exclusive. RESUM of bit6 should be
set or reset in suspend status of USB only by the remote wake-up enable status due to the following
commands.
Set USTP of bit4 to "1" before entering the stop mode state.
To deselect the stop mode, set the order of SUSP in the UDCS and USTP in the UDCC to "0".
The following describes the function of each bit in the UDC control register (UDCC).
[bit15 to bit8] Reserved bits
These bits are reserved bits. Please write "0". The bit always reads "0".
[bit7] RST: Function reset bit
Apply an individual reset that is equivalent to the system reset to the chip to the USB Function. Apply a
reset to the USB Function with the RST bit when connecting a cable to the HOST PC. Since the RST
bit has the initial value of "1" and the USB Function is in reset status, release the Function by writing
"0" to the bit.
RST
CM44-10137-6E
Figure 11.3-3 UDC Control Register (UDCC)
6
5
RESUM
HCON
USTP
0
1
R/W
R/W
14
13
Reserved
Reserved
Reserved
0
0
-
-
0
1
FUJITSU MICROELECTRONICS LIMITED
4
3
2
Reserved
Reserved
0
0
0
R/W
-
-
12
11
10
Reserved
Reserved
0
0
0
-
-
-
Operating mode
Reset of USB Function release
Reset USB Function
CHAPTER 11 USB FUNCTION
11.3 Registers of USB Function
1
0
RFBK
PWC
UDC control register
←
0
0
Initial value
←
R/W
R/W
Access
9
8
Reserved
Reserved
←
0
0
Initial value
←
-
-
Access
199
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