Hardware Interrupt Processing Time - Fujitsu MB90335 Series Hardware Manual

CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
3.4.5

Hardware Interrupt Processing Time

Before the interrupt handling routine can be executed after a hardware interrupt request
is generated, the time to complete of the currently active instruction and the interrupt
handling time are required.
■ Hardware Interrupt Processing Time
Before the interrupt handling routine can be executed after an interrupt request is generated and the
interrupt is accepted, the waiting time for the interrupt request sample and the interrupt handling time
(required for preparation for interrupt handling) are required. Figure 3.4-6 shows the interrupt handling
time.
Operation of CPU
Interrupt wait time
Interrupt request generation
*
●
Interrupt request sampling wait time
The wait time for an interrupt request sample refers to the time from generation of an interrupt request to
the completion of the currently active instruction. Whether or not an interrupt request is present is
determined by interrupt request sampling in the final cycle of each instruction. Because the CPU cannot
recognize the interrupt request for the above reason, the wait time is produced.
The wait time for an interrupt request sample reaches the maximum if an interrupt request is generated
immediately after the start of the PCPW, PW0,..., RW7 instructions with the longest cycle of execution (45
machine cycle).
●
Interrupt handling time (θ machine cycle)
The CPU must save the dedicated registers in the system stack, fetch the interrupt vectors, and execute
other processes by acceptance of the interrupt request. To do so, it requires the interrupt handling time with
the θ machine cycles. The interrupt handling time can be calculated by the expression shown below.
• When an interrupt is activated: θ = 24 + 6 x Z machine cycles
• When an interrupt is returned: θ = 11 + 6 x Z machine cycles (RETI instructions)
68
Figure 3.4-6 Interrupt Processing Time
Normal instruction execute
Interrupt request
sampling wait time
: The last cycle, Sampling interrupt request here
: 1 machine cycle is appropriate 1 clock cycle of machine clock (φ).
FUJITSU MICROELECTRONICS LIMITED
Interrupt handling
Interrupt handling time
(φ machine cycle)*
MB90335 Series
Interrupt
processing routine
CM44-10137-6E