Fujitsu MB90335 Series Hardware Manual page 419

CHAPTER 18 UART
18.4 Register of UART
Table 18.4-3 Description of Each Bit of the Serial Status Registers 0, 1 (SSR0, SSR1) (1 / 2)
Bit name
PE:
bit15 Parity error flag
bit
ORE:
bit14 Overrun error flag
bit
FRE:
bit13 Framing error
flag bit
RDRF:
bit12 Receive Data full
flag bit
TDRE:
bit11 Transmission data
empty flag bit
BDS:
bit10 Transfer direction
selection bit
RIE:
Reception
bit9
interrupt request
enable bit
398
• Detect a parity error of receiving data.
• This bit is set to "1" when a parity error occurs.
• This is cleared by writing "0" in the receiving error clear bit (SCR0, SCR1: REC).
• When receiving interrupts are enabled (SCR0, SCR1: RIE=1), a receiving interrupt
request is generated if a parity error occurs
• When the parity error flag bit is set (SSR0, SSR1: PE = 1), data in serial input data
register is invalid.
• Detect an overrun error in receiving.
• This bit is set to "1" when an overrun error occurs.
• This is cleared by writing "0" in the receiving error flag clear bit (SCR0, SCR1: REC).
• When receiving interrupts are enabled (SSR0, SSR1: RIE=1), a receiving interrupt
request is generated if a overrun error occurs.
• When the overrun error flag bit is set (SSR0, SSR1: ORE = 1), data in serial input data
register is invalid.
• Detect a framing error of receive data.
• This bit is set to "1" when a framing error occurs.
• This is cleared by writing "0" in the receiving error clear bit (SCR0, SCR1: REC).
• When receiving interrupts are enabled (SSR0, SSR1: RIE=1), a receiving interrupt
request is generated if a framing error occurs.
• When the framing error flag bit is set (SSR0, SSR1: FRE = 1), data in serial input data
register is invalid.
• Show the status of the serial input data register.
• When received data is loaded to serial input data register 0, 1 (SIDR0, SIDR1), "1" is set.
• This bit is cleared to "0" when data is read from the serial input data register 0, 1 (SIDR0,
SIDR1).
• When receiving interrupts are enabled (SSR0, SSR1: RIE=1), a receiving interrupt
request are generated if receiving data is loaded to the serial input data registers (SIDR0,
SIDR1).
• Show the status of the serial output data register 0, 1 (SODR0, SODR1).
• The bit is cleared to "0" by writing sending data to the serial output data registers 0, 1
(SODR0, SODR1).
• This bit is set to "1" when data is loaded to the send shift register and transmission starts.
• When sending interrupts are enabled (SSR0, SSR1: TIE=1) and if the data that has
written to the serial output data registers 0, 1 (SODR0, SODR1) is transferred to the
sending shift register, then a sending interrupt request is generated.
• This bit sets the direction of serial data transfer.
• When set to "0": Serial data is transferred from the LSB bit first (LSB first).
• When set to "1": Serial data is transferred from the MSB bit first (MSB first).
Note:
If BDS bit is rewritten after the completion of the access to the register, the rewritten
data will be invalid, since in reading to the serial input data register and in writing to
the serial output data register, the LSB data and the MSB data are turned upside
down.
• Enable or disable receive data.
• When set to "1": If receiving data is loaded to the serial input data registers 0, 1 (SSR0,
SSR1: RDRF=1). Or if an receiving error occurs (SSR0, SSR1:PE=1, or
ORE=1, or FRE=1), then a receiving interrupt request is generated.
FUJITSU MICROELECTRONICS LIMITED
MB90335 Series
Functions
CM44-10137-6E