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MB90335 Series
[bit4] PIE0: ppg Interrupt Enable (interrupt to PPG0/PPG2 enabled)
PPG0/PPG2 interrupt inhibition and permission are controlled.
PIE0
0
1
• If PUF0 is changed to "1" while this bit is "1", an interrupt request is generated. If this bit is "0", no
interrupts are generated.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit3] PUF0: ppg Underflow Flag (PPG0/PPG2 counter underflow)
Detected result of counter underflow of the PPG0/PPG2 is shown.
PUF0
0
1
In the 8-bit PPG 4channel mode (PPG0, PPG1/PPG2, PPG3) and the 8-bit prescaler + 8-bit PPG mode, the
counter values of ch.0, ch.2 are set to "1" when they underflow from 00
2 channel mode (PPG0, PPG1/PPG2, PPG3), the counter values of ch.1, ch.3/ch.0, ch.2 are set to "1" when
they underflow from 0000
significant. "1" is read with a read-modify-write instruction.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit2, bit1] Undefined bits
The read value is undefined. Nothing is affected when it is written.
[bit0] Reserved bit
It is Reserved bit. Always set this bit to "1".
CM44-10137-6E
The PPG counter underflow is not detected.
The PPG counter underflow was detected.
to FFFF
. Becomes "0" by written "0". "1" writing in the PUF0 bit is not
H
H
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 15 8/16-BIT PPG TIMER
15.2 Registers of 8/16-bit PPG Timer
Operating State
Disables the interrupt
Interruption permission
Operating State
to FF
. In the 16-bit PPG
H
H
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