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MB90335 Series
●
Transmission Interrupt
When sending data is sent from the serial output data registers 0, 1 (SODR0, SODR1) to the sending shift
register, then the sending data empty flag bit (SSR0, SSR1: TDRE) is set to "1". When sending interrupts
are enabled (SSR0, SSR1: TIE=1), a sending interrupt request is generated.
■ Interruption of UART, EI
Table 18.5-2 Interruption of UART, EI
Interrupt cause
UART1
Reception Interrupt
UART1
Transmission Interrupt
UART0
Reception Interrupt
UART0
Transmission Interrupt
: Available; with a function that stops EI
❍
: Available
2
■ UART EI
OS Function
UART has the circuit of the EI
occasion of each of the send interrupt and the receive interrupt.
●
At Transmission/Reception
At transmission / reception, EI
CM44-10137-6E
2
OS, and μDMAC
2
OS, and μDMAC
Interrupt control register
Interrupt
number
Register
Name
#39(27
)
0000BE
ICR14
H
#37(25
)
0000BD
ICR13
H
#39(27
)
0000BE
ICR14
H
#37(25
)
0000BD
ICR13
H
2
OS by detecting a UART receive error
2
2
OS is available regardless of the states of any other peripherals.
FUJITSU MICROELECTRONICS LIMITED
Vector table address
Address
Low
FFFF60
FFFF61
H
H
FFFF68
FFFF69
H
H
FFFF60
FFFF61
H
H
FFFF68
FFFF69
H
H
OS correspondence. This allows EI
CHAPTER 18 UART
18.5 UART Interrupt
EI
High
Bank
FFFF62
H
H
❍
FFFF6A
H
H
FFFF62
H
H
❍
FFFF6A
H
H
2
OS to start up separately on the
μDMAC
2
Channel
OS
number
12
13
12
13
405
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