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MB90335 Series
Note:
The machine clock selection bit (MCS) is initialized by reset to main clock selection.
Table 5.3-1 Functions of Clock Select Register (CKSCR) Bits
Bit name
Reserved:
bit15
Reserved bit
MCM:
bit14
PLL Clock
display bit
WS1, WS0:
Oscillation
bit13,
stabilization
bit12
wait time
selection bits
Reserved:
bit11
Reserved bit
MCS:
bit10
PLL clock
selection bit
CS1, CS0:
bit9,
Multiplier
bit8
selection bits
HCLK: Oscillation clock
CM44-10137-6E
The bit always returns "1" when read.
• Bit indicating the main or PLL clock, whichever selected as the machine clock.
• A "0" in this bit indicates that the PLL clock has been selected. A "1" in the bit indicates that
the main clock has been selected.
• If the PLL clock selection bit (MCS) = 0 and MCM = 1, now is the PLL clock oscillation
stabilization wait time.
• Writing this bit has no effect on operation.
• These bits are used to select an oscillation stabilization wait time required for the oscillation
clock when the stop mode is canceled.
• Initialized to "11
" by every reset cause.
B
Note:
The oscillation stabilization wait time must be set to a suitable value for the oscillator to use. See
"4.2 Reset Factors and Oscillation Stabilization Wait Times". Please set the setting of "00
at the main clock mode.
Reference:
The oscillation stabilization wait time for PLL clock is fixed to 2
Be sure to set this bit to "1".
• Bit for selecting main or PLL clock as the machine clock.
• A "0" in this bit selects the PLL clock. A "1" in the bit selects the main clock.
• If "0" is written to this bit when it is "1", the PLL clock oscillation stabilization wait time is
produced, thereby clearing the time-base timer automatically. Also, the interrupt request flag
bit (TBOF) of the time-base timer control register (TBTC) is cleared.
• The PLL clock oscillation stabilization wait time is fixed to 2
is 6 MHz, the oscillation stabilization wait time will be approximately 2.73 ms.)
• If the main clock is selected, the operating clock frequency will be the oscillation clock
frequency-divided by 2. (If the oscillation clock is 6 MHz, the operating clock will be 3 MHz.)
• Initialized to "1" by every reset cause.
Note:
To write "0" if when MCS bit is "1", make sure that the time-base timer interrupt have been
masked using the TBTC register interrupt request enable bit (TBIE) or interrupt level mask
register (ILM).
• Bit for selecting the multiply factor for PLL clock.
• The multiplier can be selected from among three options.
• Initialized to "00
" by every reset cause.
B
Note:
When the MCS or MCM is "0", writing to these bits is not allowed. Rewrite the CS1 and CS0 bits
after setting the MCS bit to "1" once. "11
FUJITSU MICROELECTRONICS LIMITED
5.3 Clock Select Register (CKSCR)
Functions
14
/HCLK.
14
/HCLK. (If the oscillation clock
" is a set interdiction.
B
CHAPTER 5 CLOCK
" only
B
129
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