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APPENDIX B Instructions
2
B.8 F
MC-16LX Instruction List
Table B.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
ANDL
A,ear
ANDL
A,eam
2+
ORL
A,ear
ORL
A,eam
2+
XORL
A,ear
XORL
A,eam
2+
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.
Table B.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
NEG
ear
NEG
eam
2+
NEGW
A
NEGW
ear
NEGW
eam
2+
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
Table B.8-11 1 Normalization Instruction (Long Word)
Mnemonic
#
NRML
A,R0
2
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
568
#
~
RG
B
2
6
2
0
7+(a)
0
(d)
2
6
2
0
7+(a)
0
(d)
2
6
2
0
7+(a)
0
(d)
#
~
RG
B
1
2
0
0
2
3
2
0
2 × (b)
5+(a)
0
1
2
0
0
2
3
2
0
2 × (c)
5+(a)
0
~
RG
B
long (A) ← Shift left to the position where '1' is set
*1
1
0
for the first time.
byte (R0) ← Shift count at that time
FUJITSU MICROELECTRONICS LIMITED
Operation
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
Operation
byte (A) ← 0 - (A)
byte (ear) ← 0 - (ear)
byte (eam) ← 0 - (eam)
word (A) ← 0 - (A)
word (ear) ← 0 - (ear)
word (eam) ← 0 - (eam)
Operation
MB90335 Series
LH
AH
I
S
T
N
Z
-
-
-
-
-
*
*
-
-
-
-
-
*
*
-
-
-
-
-
*
*
-
-
-
-
-
*
*
-
-
-
-
-
*
*
-
-
-
-
-
*
*
LH
AH
I
S
T
N
Z
X
-
-
-
-
*
*
-
-
-
-
-
*
*
-
-
-
-
-
*
*
-
-
-
-
-
*
*
-
-
-
-
-
*
*
-
-
-
-
-
*
*
LH
AH
I
S
T
N
Z
-
-
-
-
-
-
*
CM44-10137-6E
V
C
RMW
R
-
-
R
-
-
R
-
-
R
-
-
R
-
-
R
-
-
V
C
RMW
*
*
-
*
*
-
*
*
*
*
*
-
*
*
-
*
*
*
V
C
RMW
-
-
-
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