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CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
21.3 Configuration of Address Match Detection Function
Table 21.3-1 Functions of Address Detection Control Register (PACSR)
Bit Name
bit7 to
Reserved: reserved bits
bit4
AD1E:
bit3
Address match
detection enable bit1
bit2
Reserved: reserved bit
AD0E:
bit1
Address match
detection enable bit0
bit0
Reserved: reserved bit
464
Always set to "0".
The address match detection operation with the detect address setting
register 1 (PADR1) is enabled or disabled.
When set to "0": Disables the address match detection operation.
When set to "1": Enables the address match detection operation.
• When the value of detect address setting registers 1 (PADR1) matches
with the value of address latch at enabling the address match detection
operation (AD1E = 1), the INT9 instruction is immediately executed.
Always set to "0".
The address match detection operation with the detect address setting
register 0 (PADR0) is enabled or disabled.
When set to "0": Disables the address match detection operation.
When set to "1": Enables the address match detection operation.
• When the value of detect address setting register 0 (PADR0) matches
with the value of address latch at enabling the address match detect
operation (AD0E = 1), the INT9 instruction is immediately executed.
Always set to "0".
FUJITSU MICROELECTRONICS LIMITED
MB90335 Series
Function
CM44-10137-6E
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