Fujitsu MB90335 Series Hardware Manual page 194

MB90335 Series
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Time-base timer counter
This is an 18-bit up-counter whose count clock is two-division clock of oscillation clock (HCLK).
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Counter clear circuit
This circuit clears the counter by writing "0" to time-base timer initialization bit (TBR) of time-base timer
control register (TBTC), power-on reset, transition to the stop mode, switching to PLL clock mode from the
main clock mode.
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Interval timer selector
This selects the output of the time-base timer counter from one of four types. The overflow of selected bit
will be the interrupt cause.
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Time-base timer control register (TBTC)
Interval time selection, counter clearance, and interrupt request control and status check are executed.
CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED
CHAPTER 9 TIME-BASE TIMER
9.2 Configuration of Time-base Timer
173