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CHAPTER 12 USB HOST
12.4 Register of USB HOST
12.4.2
Host Interruption Register (HIRQ)
The host interrupt register (HIRQ) indicates for the interrupt request flag for USB HOST.
It can allow an interrupt to be generated by setting the interrupt enable bit in the host
control registers (HCNT0/HCNT1) except the TCAN bit.
■ Host Interruption Register (HIRQ)
Figure 12.4-2 Bit Configuration of Host Interruption Register (HIRQ)
Host interruption register
bit
Address: 0000C2
H
→
Read/Write
→
Initial value
Reset On/Off at UDCC RST bit →
[bit 7] TCAN: Token cancellation flag
When the SOFIRQ bit in the host interrupt register (HIRQ) becomes "1", it indicates that a token is
cancelled without being executed once. Any interrupt is not raised because the register is combined with
interrupt due to SOF. To set it to "0", write "0" to it.
To update them, you must set the RST bit in the UDC control register (UDCC) to "0".
[bit 6] Reserved
It is reserved bit.
Be sure to set this bit to "0".
[bit 5] RWKIRQ: Reactivation interrupt request
It indicates that resume operation has been completed. When it becomes "1", it gets back to "0" by
writing "0" to it. When you write "1" to it, the current state will be preserved. If the RWKIRE bit in the
host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1". The interrupt signal is
cleared when it is cleared with "0".
To update them, you must set the RST bit in the UDC control register (UDCC) to "0".
RWKIRQ
254
7
6
5
TCAN
Reserved
RWKIRQ
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
❍
❍
❍
(
)
(
)
(
TCAN
0
There is no token discontinuance.
1
There is token discontinuance.
0
There is no interrupt request by reactivation.
1
There is an interrupt request by reactivation.
FUJITSU MICROELECTRONICS LIMITED
4
3
URIRQ
CMPIRQ
CNNIRQ
(R/W)
(R/W)
(0)
(0)
❍
❍
)
(
)
(
)
Operation mode
Operation mode
MB90335 Series
2
1
0
DIRQ
SOFIRQ
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
❍
( )
( )
(
)
CM44-10137-6E
HIRQ
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