Fujitsu MB90335 Series Hardware Manual page 253

CHAPTER 11 USB FUNCTION
11.4 Operation Explanation of USB Function
• STAL Bit Clear Timing
For STALL release, clears STAL bit at detecting SETP bit of "1" (DRQO bit = 1 for interrupt) that
indicates the set-up stage of control transfer, and sets STAL bit if the STALL response is required. (See
Figure 11.4-9.)
Token
packet
DRQO bit
SETP bit
STAL bit
For STALL response release (STAL bit clear), clear STAL bit the period between the time when SETP
bit of "1" (DRQO bit= 1 for interrupt) is detected and the time when the data packet transmission/
reception of the next data stage is started. The period between the time when DRQO becomes "1" and
the time when STAL bit is cleared is as follows: (Transfer speed: at Full speed of 12Mbps) When STAL
bit is not cleared in the following period, execute STAL response with the handshake of data stage.
The period between the time when DRQO bit of "1" is detected and the time when STAL bit is cleared:
within idle time + 2.75 μs
* When idle time is the shortest period of 2-bit transfer time, the above period is within about 2.9 μs.
If the STAL bit clear cannot executed within the above period, take an appropriate countermeasures such
as lengthening of the idle time with a driver of USB host.
■ STALL response /release of Endpoints 1 to 5
STALL response /release of Endpoints 1 to 5 are controlled with Control registers of EP1 to EP5 and
internal condition bit
• To execute STAL response with software
The procedures to execute STAL response with software are shown in Figure 11.4-10. To execute STAL
response, set STAL bit of the relevant endpoint with software. In this time, the internal condition bit
does not change. Furthermore, when a host generates a transaction to the endpoint where STAL bit is set,
hardware would automatically set the internal condition bit of the relevant endpoint and gives STALL
response to the host.
Once the internal condition bit is set, the internal condition bit has been set and continues STAL response
until Clear Feature command is issued from the host despite of the clearing of STAL bit.
As long as the STAL bit is set, STAL bit response continues even if the internal condition bit is cleared
with Clear Feature command because the internal condition bit is set every time a transaction to the
relevant endpoint occurs. Therefore, to release the STAL response, be sure to clear STAL bit and the
internal condition bit with the Clear Feature command.
232
Figure 11.4-9 STAL Bit Clear Timing
Set-up stage
Data Handshake
packet packet
FUJITSU MICROELECTRONICS LIMITED
Idle time
Token
packet
STAL bit clear timing
Within idle time and 2.75 μs
MB90335 Series
Data stage
Data Handshake
packet packet
CM44-10137-6E