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MB90335 Series
A sample flow is given below.
*: When "arbitration lost" is detected, the MSS bit is set to "1" and then the AL bit is set to "1" without failure
after the time for three-bit data transmission at the I
•
Example of occurrence of an interrupt (INT bit=1) upon detection of "AL bit=1"
When an instruction which generates a start condition is executed (setting the MSS bit to "1") with "bus
busy" detected (BB bit=1) and arbitration is lost, the INT bit interrupt occurs upon detection of "AL
bit=1".
Figure 19.2-6 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" Occurs
SCL0 pin
SDA0 pin
EN pin
MSS pin
AL pin
BB pin
INT pin
CM44-10137-6E
Master mode setting
Set the MSS bit in the bus control register (IBCR0) to "1".
Wait* for the time for three-bit data transmission at the I
transfer frequency set in the clock control register (ICCR0).
BB bit=0 and AL bit=1?
YES
Set the EN bit to
Start Condition
SLAVE ADDRESS
FUJITSU MICROELECTRONICS LIMITED
NO
to normal process
2
0
to initialize I
C
"
"
2
C transfer frequency.
Interrupt in the ninth clock cycle
ACK
DATA
Clearing the AL bit by software
Releasing the SCL0 by clearing
the INT bit by software
2
CHAPTER 19 I
C INTERFACE
2
19.2 I
C Interface Register
2
C
441
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