Fujitsu MB90335 Series Hardware Manual page 81

CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
■ Construction of Hardware Interrupt
As shown in Table 3.4-1, there are four features related to hardware interrupt. These four must be
programmed when hardware interrupt is used.
Table 3.4-1 Mechanism Related to Hardware Interrupt
Peripheral function
Interrupt controller
CPU
FFFC00 to FFFFFF in
H H
memory
■ Hardware Interrupt Suppression
For hardware interrupt, acceptance of the interrupt request is suppressed in the following conditions:
●
Suppressing a hardware interrupt which is generated during write to a peripheral function control
register area
While data is being written to a peripheral function control register area, no hardware interrupt request is
accepted. The purpose of this is to prevent the CPU from causing a malfunction due to some interrupt-
related problem in response to an interrupt request which is generated while the interrupt control register
relation for each resource is being rewritten. The peripheral function control register area is the area
assigned to the control and data registers of the peripheral function control registers. Note that they are not
the 000000
Figure 3.4-1 shows the hardware interrupt operation which takes place during write to the peripheral
function control register area.
Figure 3.4-1 Hardware Interrupt Request during Write to the Peripheral Function Control Register Area
60
Mechanism related to hardware
interrupt
Interrupt enable bits, interrupt request
bits
Interrupt control registers (ICR)
Interrupt enable flag (I)
Interrupt level mask register (ILM)
Microcode
Interrupt vector table
to 0000FF I/O addressing area.
H H
Instruction of writing to peripheral function control register area
MOV A.#08
generating interrupt
request here
FUJITSU MICROELECTRONICS LIMITED
Controls interrupt request from peripheral function
Setting interrupt levels
Identification of interrupt enable state
Compares request interrupt level and current
interrupt level
Execution of interruption handling routine
Stores the branch destination address at interrupt
processing
MOV io,A
MOV A,2000H
not branch
to interrupt
MB90335 Series
Functions
Interrupt
processing
branch
to interrupt
CM44-10137-6E