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CHAPTER 5 CLOCK
5.4 Clock Mode
5.4
Clock Mode
The clock modes are the main clock mode and PLL clock mode.
■ Main Clock Mode, PLL Clock Mode
●
Main clock mode
The main clock mode stops the PLL clock by using an oscillation clock frequency divided by 2 as the
operating clock of the CPU and peripheral resources.
●
PLL clock mode
The PLL clock mode uses the PLL clock as operation clock for the CPU and peripheral functions. The PLL
clock frequency multiplier factor can be selected using the clock selection register (CKSCR).
Note:
To use the USB HOST or USB function, the PLL clock mode must have been set.
■ Transition of Clock Mode
Writing the PLL clock selection bit (MCS) of the CKSCR changes the clock mode to main or PLL.
●
Transition from main clock mode to PLL clock mode
If the CKSCR of MCS bit is rewritten from "1" to "0" while in the main clock mode, the mode will change
from main to PLL after the PLL clock oscillation stabilization wait time (2
●
Transition from PLL clock mode to main clock mode
If the CKSCR of MCS bit is rewritten from "0" to "1" while in the PLL clock mode, the mode will change
from PLL to main when the PLL and main clock edges will match (after 1 to 8 PLL clocks).
Note:
Even if the PLL clock selection (MCS) bit of the CKSCR is rewritten, the machine clock is not
switched immediately. If a resource which depends on the machine clock needs to be operated, refer
the PLL clock indicator bit (MCM) of the CKSCR to check that the machine clock has been switched,
before beginning the operation.
If the clock mode is switched, the mode must not be switched to another clock mode or the low-
power consumption mode until completion of the switching. Completion of the switching can be
checked by referring the MCM bit of the CKSCR.
■ Selection of PLL Clock Multiplication Rate
One of the three PLL clock frequency multiplier from 1 to 4 times can be selected by writing "00
"10
" to the CS1 and CS0 bits of the CKSCR. "11
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FUJITSU MICROELECTRONICS LIMITED
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MB90335 Series
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