Fujitsu MB90335 Series Hardware Manual page 196

MB90335 Series
Table 9.3-1 Time-base Timer Control Register (TBTC)
Bit name
Reserved:
bit15
Reserved bit
bit14,
Unused bits
bit13
TBIE:
bit12 Interrupt request
enable bit
TBOF:
bit11 Interrupt request
flag bit
TBR:
bit10 Time-base timer
initialization bit
TBC1, TBC0:
bit9,
Interval time
bit8
select bits
CM44-10137-6E
Note:
Be sure to write "1".
• The value at the time of reading is irregular.
• No effect on writing.
• This bit permits or prohibits an interrupt request output to the CPU.
• If the TBIE bit and interrupt request flag bit (TBOF) is set to "1", an interrupt request is
output.
• An overflow of time-base timer counter specification bit sets the status to "1".
• If the TBOF bit and interrupt request permission bit (TBIE) is set to "1", an interrupt request
is output.
Setting to "0" executes clearance during writing and no changes are made at "1", making no
influences on others.
Notes:
• When clearing the TBOF bit, set to the condition that prohibits time-base timer interrupt
with the interrupt request permission bit (TBIE) or by specifying interrupt level mask
register (ILM) in processor status (PS).
• The status is cleared to "0" by "0" writing, transition to the stop mode, transition from the
main clock mode to the PLL clock mode, "0" writing to time-base timer initialization bit
(TBR), or resetting.
• This bit clears the time-base timer counter.
• Writing "0" clears the counter, immediately after that, clears the TBOF bit. No changes are
made at "1", making no influences on others.
Reference:
Always read value is "1".
• These bits specify a cycle for the interval timer.
• The bit for the interval timer of time-base timer counter is specified.
• One of four interval time can be selected.
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 9 TIME-BASE TIMER
9.3 Time-base Timer Control Register (TBTC)
Functions
175