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MB90335 Series
■ Operation of Software Interrupt
Figure 3.5-1 shows the operation sequence from generation of a software interrupt to completion of
interrupt handling.
Internal bus
PS : Processor status
I
: Interrupt enable flag
S : Stack flag
IR : Instruction register
(1) Software interrupt instruction is executed.
(2) The required processes are performed; for example, the contents of the dedicated registers are saved
according to the microcode associated with the software interrupt instruction. The branching process is
then executed.
(3) The RETI instruction in the user-defined interrupt handling routine terminates the interrupt handling.
■ Precautions on Software Interrupt
If the program counter bank register (PCB) is "FF
with the table for the INT#vct8 instruction. When creating the software, pay attention to overlap of the
CALLV instruction and INT#vct8 instruction addresses.
CM44-10137-6E
Figure 3.5-1 Operation of Software Interrupt
PS, PC
(2) Microcode
RAM
FUJITSU MICROELECTRONICS LIMITED
PS
(1)
IR
Queue
", the vector area for the CALLV instruction overlaps
H
CHAPTER 3 INTERRUPT
3.5 Software Interrupt
I
S
Fetch
71
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