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APPENDIX A Memory Map
Table A-1 I/O Map (3 / 8)
Address
00005C
H
PWC Control Status Registers
00005D
H
00005E
H
PWC data buffer register
00005F
H
000060
PWC ratio of dividing frequency control register
H
000061
H
000062
H
Timer control status register 0
000063
H
Low order of 16-bit timer register 0
000064
H
Low order of 16-bit reloading 0
High order of 16-bit timer register 0
000065
H
High order of 16-bit reloading 0
000066
H
to
00006E
H
00006F
ROM Mirroring Function Select Register
H
000070
2
I
C bus status register 0
H
2
000071
I
C bus control register 0
H
000072
2
I
C bus clock control register 0
H
2
000073
I
C bus address register 0
H
000074
2
I
C bus data register 0
H
000075
H
to
00009A
H
DMA descriptor channel specification
00009B
H
register
00009C
Low order of DMA status register
H
00009D
Low order of DMA status register
H
Program address detection control status
00009E
H
register
Delay interruption factor generation/release
00009F
H
register
Low-power consumption mode control
0000A0
H
register
0000A1
Clock select register
H
0000A2
H
to
0000A3
H
0000A4
DMA stop status register
H
528
Registers
FUJITSU MICROELECTRONICS LIMITED
Abbreviation
Access
PWCSR
R/W,R
PWCR
R/W
DIVR
R/W
Use prohibited
TMCSR0
R/W
TMR0
R
TMRLR0
W
TMR0
R
TMRLR0
W
Use prohibited
ROMM
R/W, W
IBSR0
R
IBCR0
R/W
ICCR0
R/W
IADR0
R/W
IDAR0
R/W
Use prohibited
DCSR
R/W
DSRL
R/W
DSRH
R/W
PACSR
R/W
DIRR
R/W
LPMCR
R/W, W
CKSCR
R/W, R
Use prohibited
DSSR
R/W
MB90335 Series
Release
Initial value
00000000
0000000X
00000000
16-bit PWC timer
00000000
------00
00000000
XXXX0000
XXXXXXXX
16bit reload timer
ch.0
XXXXXXXX
XXXXXXXX
XXXXXXXX
ROM mirror
------11
function
00000000
00000000
2
XX0XXXXX
I
C interface ch.0
XXXXXXXX
XXXXXXXX
00000000
μDMAC
00000000
00000000
Address compare
00000000
detection
-------0
Delayed interrupt
Low power
00011000
consumption
11111100
Clock
μDMAC
00000000
CM44-10137-6E
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
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