Fujitsu MB90335 Series Hardware Manual page 116

MB90335 Series
3.8.3.1 DMA Data Counter (DDCTH/DDCTL)
DMA data counter (DDCTH/DDCTL) sets the data transfer.
When DDCTH/DDCTL is "0000
■ DMA Data Counter (DDCTH/DDCTL)
DMA data counter (DDCTH/DDCTL), a 16-bit length register, indicates the counter associated with
transferred number. After each data has been transferred, the counter is always decremented by 1 regardless
of transferred data (word or byte). The DMA transfer ends when this counter reaches 0000
shows the DDCT configuration.
If the DDCT is set to "0000
Figure 3.8-7 Bit Configuration of DMA Data Counter (DDCTH/DDCTL)
007927 /007926
H
bit15
DDCTH/
B15
DDCTL
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W: Readable/Writable
X: Undefined
■ About the Set Value of DMA Data Counter (DDCTH/DDCTL)
Table 3.8-2 shows the relationship between the number of transferred bytes and the DDCTH/DDCTL.
Table 3.8-2 Set Value of DMA Data Counter (DDCTH/DDCTL)
N: Number of transfer bytes
CM44-10137-6E
", the DMA transfer ends.
H
", the maximum data transfer count (65536) is set.
H
H
DDCTH
bit14 bit13 bit12 bit11 bit10 bit9
B14 B13 B12 B11 B10 B09
DMACS
BW bit
0
1
1
FUJITSU MICROELECTRONICS LIMITED
DDCTL
bit8 bit7 bit6 bit5 bit4 bit3
B08 B07 B06 B05 B04 B03
BYTEL bit
-
0
1
CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
bit2 bit1 bit0
Initial value
B02 B01 B00
XXXX
H
DDCT
N
N/2
(N+1)/2
. Figure 3.8-7
H
95