Ep1 To Ep5 Control Register (Ep1C To Ep5C) - Fujitsu MB90335 Series Hardware Manual

CHAPTER 11 USB FUNCTION
11.3 Registers of USB Function
11.3.3

EP1 to EP5 Control Register (EP1C to EP5C)

EP1 to EP5 control register (EP1C to EP5C) controls concerning end point 1 to end
point 5.
■ EP1 to EP5 Control Register (EP1C to EP5C)
Figure 11.3-5 shows the bit configuration of the EP1 to EP5 control register (EP1C to EP5C).
Address bit 7
EP1C 0000D4
H
0
R/W
Address bit 7
Reserved
EP2C 0000D6
H
0
EP3C 0000D8
H
EP4C 0000DA
H -
EP5C 0000DC
H
Address bit 15
EP1C 0000D5
EPEN
H
0
R/W
Address bit 15
EP2C 0000D7
EPEN
H
EP3C 0000D9
H
0
EP4C 0000DB
H
R/W
EP5C 0000DD
H
R/W : Readable/Writable
Note:
Ensure that you must set the EP1 to EP5 control registers (EP1C to EP5C), except DMAE, NULE,
and STAL, when both bit7 RST of the UDC control register (UDCC) and bit15 BFINI of the EP0 to
EP5 status registers (EP1S to EP5S) are "1" and must not rewrite them while the USB is operating.
The following describes the function of each bit in the EP1 to EP5 control register (EP1C to EP5C).
[bit15] EPEN: End Point 1 to End Point 5 permission bit
The end point is made effective. Setting the EPEN bit allows it to be configures by the host as an end
point for use in the USB Function. TYPE, DIR, and PKS of the EP1 to EP5 control registers become
valid for configuration information.
204
Figure 11.3-5 EP1 to EP5 Control Register (EP1C to EP5C)
6 5
0 0
R/W R/W
6 5
1 0
R/W R/W
14 13
TYPE
1 1
R/W R/W
14 13
TYPE
1 1
R/W R/W
FUJITSU MICROELECTRONICS LIMITED
4 3 2
PKS1
0 0 0
R/W R/W R/W
4 3 2
PKS5 to PKS2
0 0 0
R/W R/W R/W
12 11 10
DIR DMAE NULE
0 0 0
R/W R/W R/W
12 11 10
DIR DMAE NULE
0 0 0
R/W R/W R/W
MB90335 Series
1 0
←
0 0 Initial value
←
R/W R/W Access
1 0
←
0 0
Initial value
←
R/W R/W Access
9 8
STAL PKS1
←
0 1
Initial value
←
R/W R/W Access
9 8
STAL Reserved
←
0 0 Initial value
←
R/W - Access
CM44-10137-6E