Udc Status Register (Udcs) - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
11.3.5

UDC Status Register (UDCS)

The UDC status register (UDCS) is a register that indicates the status of a bus on USB
communications and a particular command received. Each bit in the register except
SETP indicates an interrupt factor and raises an interrupt to CPU if its corresponding
interrupt enable bit is specified and valid.
■ UDC Status Register (UDCS)
Figure 11.3-7 shows the bit configurations of the UDC status register (UDCS).
Address bit 7
0000E0
-
H
X
X
-
R/W : Readable/Writable
The function of each bit in the UDC status register (UDCS) is described in the following.
[bit7, bit6] Undefined bits
Writing has no effect on the operation. Reading is undefined.
[bit5] SUSP: Suspend detection bit
It displays the fact that the USB Function shifts to suspend status. The SUSP bit is an interrupt factor
and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write.
SUSP
0
1
[bit4] SOF:SOF reception detection bit
It indicates that an SOF packet has been received, and the value of the time stamp register is updated.
The SOF bit is an interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at
the read modification write.
SOF
0
1
CM44-10137-6E
Figure 11.3-7 UDC Status Register (UDCS)
6 5 4
- SUSP SOF
X 0 0
X 0 0
- R/W R/W
Suspend undetection and interruption clear factor
Suspend detection
SOF unreception and interruption clear factor
The SOF packet is received.
FUJITSU MICROELECTRONICS LIMITED
3 2 1
BRST WKUP SETP
0 0 0
0 0 0
R/W R/W R/W
Operating mode
Operating mode
CHAPTER 11 USB FUNCTION
11.3 Registers of USB Function
0
CONF UDC status register
←
0
Initial value
←
0 RST Reset
←
R/W
Access
209