Fujitsu MB90335 Series Hardware Manual page 401

CHAPTER 17 EXTENDED I/O SERIAL INTERFACE
17.3 Operation of Extended I/O Serial Interface
●
Transfer State
It is a state to do the serial transfer by BUSY = 1. MODE bit triggers the transition to the state of HALT
and R/W WAIT respectively.
Figure 17.3-1 shows the transition diagram of each state, and Figure 17.3-2 shows the conceptual diagram
of read/write of the serial data register.
Figure 17.3-1 Transition Diagram of Operation in Extended I/O Serial Interface
Stop state (Transfer complete)
STRT=0, BUSY=0
MODE=0
MODE=0
STOP=0
&
STOP=0
STRT=1
Transfer operation
STRT=1, BUSY=1
Figure 17.3-2 Conceptual Diagram of Reading/writing Serial Data Register
SOT
SIN
Interrupt output
Extended I/O
serial interface
(1) When MODE=1, transfer is terminated by the shift clock counter. This allows SIR=1 to go into read/
write state. If the SIE bit is "1", the interruption signal is generated. However, when SIE is inactive, or
when writing "1" in STOP causes the suspend of transfer, interrupt signals are not generated.
(2) Once the serial data register is read or written, interrupt requests are cleared, and serial transfer starts.
380
STOP=0 & STRT=0
& STOP=1
&
END
MODE=1 & END & STOP=1
SDR R/W & MODE=1
Data bus
Read
Write
(2)
FUJITSU MICROELECTRONICS LIMITED
STOP=1
STOP=0
&
STRT=1
Serial data register R/W wait
Data bus
Read
Write
(1)
Interrupt input
Data bus
MB90335 Series
Reset
STOP
STRT=0, BUSY=0
STOP=1
STRT=1, BUSY=0
MODE=1
CPU
Interrupt
controller
CM44-10137-6E