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CHAPTER 18 UART
18.7 Explanation of Operation of UART
●
Specification of serial clock output level at inoperative
Serial clock output level (SMR: SCKL) at the clock synchronous mode and inoperative can be set.
Figure 18.7-4 Setting of Serial Clock Output Level at Inoperative
Transfer data write
Transfer/receive
clock
(SCKL=1)
Transfer/receive
clock
(SCKL=0)
RXE, TXE
Transfer data
●
Error detection
Only overrun errors can be detected. Parity and framing errors cannot be detected.
●
Initialization
The setting value of each control register is described when using the synchronous mode.
[Serial mode register 0, 1 (SMR0, SMR1)]
MD1, MD0
SCKL
M2L2 to M2L0 :If 8-bit transmission is specified, set to "000
SCKE
SOE
420
1
0
:"10
"
B
:If the level of the serial clock output in the inactive operating state is "H", set to "1"
:If the level of the serial clock output in the inactive operating state is "L", set to "0".
:If 7-bit transmission is specified, set to "111
:If 6-bit transmission is specified, set to "110
:If 5-bit transmission is specified, set to "101
:If 4-bit transmission is specified, set to "100
:If 3-bit transmission is specified, set to "011
:If 2-bit transmission is specified, set to "010
:If 1-bit transmission is specified, set to "001
: "1" for the dedicated baud rate generator, "0" for the clock output and the external
clock (clock input).
: "1" for transmitting, "0" only in case of reception
FUJITSU MICROELECTRONICS LIMITED
1
1
0
0
1
0
".
B
".
B
".
B
".
B
".
B
".
B
".
B
".
B
MB90335 Series
Mark level
CM44-10137-6E
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