Table of Contents
Advertisement
MB90335 Series
[bit8] INT: INTerrupt
It is transfer stop interrupt request flag bit.
(at writing)
0
1
(at reading)
0
1
The SCL0 line is kept at "L" level at "1". Is cleared by writing "0", releases SCL0 line, and sends the
subsequent bite. And is reset to "0" by occurrence of the start condition or the stop condition on the master
connection.
Notes:
When an instruction which generates a start condition is executed (the MSS bit is set to "1") at the timing
shown in Figure 19.2-4 and Figure 19.2-5, arbitration lost detection (AL bit=1) prevents an interrupt (INT
bit=1) from being generated.
•
Condition 1 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur.
When an instruction which generates a start condition is executed (setting the MSS bit in the IBCR0
register to "1") with no start condition detected (BB bit=0) and with the SDA0 or SCL0 pin at the "L" level.
Figure 19.2-4 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur
SCL0 pin
SDA0 pin
2
I
C operation enable state (EN bit=1)
Master mode setting (MSS bit=1)
Arbitration lost detection (AL bit=1)
Bus busy (BB bit)
Interrupt (INT bit)
CM44-10137-6E
Clear Transfer stop interrupt request flag.
No effect on operation
Transfer has not been finished yet.
This is set when 1 byte of data including the ACK bit has already been transferred and if
the following condition is applied.
• It is a bus master.
• It is a slave that the address is done.
• The General call address was received.
• The arbitration lost happened.
• Other systems tried to generate a start condition while the bus was in use.
SCL0 or SDA0 pin at "L" level
FUJITSU MICROELECTRONICS LIMITED
2
CHAPTER 19 I
C INTERFACE
2
19.2 I
C Interface Register
"L"
"L"
1
0
0
439
Advertisement
Table of Contents
