Start/Stop Timing Of Shift Operation And Timing Of I/O - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
17.3.3

Start/Stop Timing of Shift Operation and Timing of I/O

Start/stop timing of shift operation and timing of I/O is described.
■ Start/stop Timing of Shift Operation and Timing of I/O
• Start
STOP bit of Start SMCS is set to "0", while STRT bit to "1".
• Stop
One halt is triggered from the termination of transfer; the other from STOP=1.
- Halt from STOP=1: Halts staying with SIR=0, regardless of MODE bit.
- Halt from transfer termination: Halts with SIR=1, regardless of MODE bit.
Regardless of MODE bit when BUSY bit is in the state of serial transfer, it is set to "1", and when in HALT
or R/W WAIT state, it is set to "0". Please read this bit to confirm forwarding.
The following chart shows the operation for each mode and the timing of halt operation. DO7 to DO0 in
figure shows output data.
●
Internal shift clock mode (LSB first)
Figure 17.3-3 Start/stop Timing of Shift Operation (Internal Clock)
SCK
(Transfer start)
STRT
BUSY
SOT
●
External shift clock mode (LSB first)
Figure 17.3-4 Start/stop Timing of Shift Operation (External Clock)
SCK
STRT
BUSY
SOT
CM44-10137-6E
MODE=0
DO0
(Transfer start)
MODE=0
DO0
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 17 EXTENDED I/O SERIAL INTERFACE
17.3 Operation of Extended I/O Serial Interface
"1" Output
(Transfer complete)
DO7
(Data hold)
(Transfer complete)
DO7 (Data hold)
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