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MB90335 Series
[bit11] OVIR (timer overflow interrupt request flag)
This flag indicates the 16-bit up count timer overflowed from FFFF
overflow interrupt factor is permitted (bit10: OVIE = 1) and this bit is set, the timer overflow interrupt
request occurs.
OVIR
Set factor
Clear factor
• Initialized to "0" at reset.
• Reading and writing are allowed; however, only writing "0" is effective, while writing "1" causes no
changes in the bit value.
• The read value is "1" in the read-modify write instructions regardless of the bit value.
[bit10] OVIE (timer overflow interrupt request permission)
Measurement termination interrupt request during the pulse width measurement is controlled as shown
in the table below:
OVIE
0
Overflow interrupt request output disabled (interrupt is not generated even if OVIR is set). [Initial value]
1
Overflow interrupt request output enabled (interrupt is generated when OVIR is set).
• Initialized to "0" at reset.
• Reading and writing are allowed.
[bit9] ERR (error flag)
This flag indicates the next measurement termination before reading the measured result in the PWCR
in the pulse width measurement in the continuous measurement mode. In this case, the PWCR value is
updated with the new measurement result and the previous measurement result is lost. The
measurement is continued regardless of the bit value.
ERR
Set factor
Set when measurement results that are not read yet are erased due to the next result.
Clear factor
Because PWCR (measurement result) is read, it is clear.
• Initialized to "0" at reset.
• Only reading is allowed. Write operations have no effect.
[bit8] Reserved bit
It is Reserved bit. Be sure to write "0".
CM44-10137-6E
Set when the overflow generates (FFFF
It is clear because of "0" writing or μDMAC.
Operation mode
Operation mode
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 13 PWC TIMER
13.2 Register of PWC Timer
H
Operation mode
to 0000
).
H
H
to 0000
. When the timer
H
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