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MB90335 Series
12.4.9
FRAME Setting Register (HFRAME)
The FRAME setting register (HFRAME) is a register that sets a FRAME Number in
handling SOF tokens. When you set the TKNEN bits of the host token endpoint register
(HTOKEN) to SOF activation, the SOF timer starts and, afterwards, an SOF is
automatically sent out every 1 ms. The FRAME setting register is automatically
incremented by 1 every time an SOF is completed.
■ FRAME Setting Register (HFRAME)
Figure 12.4-9 Bit Configuration of FRAME Setting Register (HFRAME)
FRAME setting register
bit
Address: 0000CC
H
→
Read/Write
→
Initial value
Reset On/Off at UDCC RST bit →
bit
Address: 0000CD
H
→
Read/Write
→
Initial value
Reset On/Off at UDCC RST bit →
[bit 15 to bit 11] Reserved
These are reserved bits. The reading is undefined. The writing does not influence the operation.
[bit 10 to bit 0] FRAME1, FRAME0
Frame Number is set. Before setting the TKNEN bits of the host token endpoint register (HTOKEN) to
SOF, set Frame Number. Furthermore, when the SOFBUSY bit of the host status register (HSTATE) is
"1" and an SOF token is being executed, write operation is inhibited. To update them, you must set the
RST bit in the UDC control register (UDCC) to "0".
CM44-10137-6E
7
6
5
15
14
13
Reserved
(-)
(x)
(-)
FUJITSU MICROELECTRONICS LIMITED
4
3
2
FRAME0
(R/W)
(00000000
)
B
❍
(
)
12
11
10
CHAPTER 12 USB HOST
12.4 Register of USB HOST
1
0
HFRAME
9
8
FRAME1
HFRAME
(R/W)
(000
)
B
❍
(
)
267
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