Fujitsu MB90335 Series Hardware Manual page 146

MB90335 Series
■ Clock Supply Map
Machine clocks generated by the clock generation section are supplied as operating clocks of the CPU and
peripheral function. For this reason, operation of the peripheral functions is influenced by switching clock
mode between the main and PLL clock or switching the PLL clock frequency multiplication rate. The
frequency divided output from the time-base timer is provided to some peripheral functions, thereby
enabling each periphery to select its operating clock. Figure 5.1-1 contains the map showing how the clocks
are provided.
Clock generation unit
X0
System
Pin
clock
X1
generation
HCLK
Pin
circuit
: Oscillation clock
HCLK
MCLK : Main clock
: PLL clock
PCLK
: Machine clock
CM44-10137-6E
Figure 5.1-1 Clock Supply Map
Time-base timer
1 2
4
PLL frequency
multiplication circuit
PCLK
Clock selector
2 division
MCLK
FUJITSU MICROELECTRONICS LIMITED
Peripheral function
Watchdog timer
4
16-bit
PPG timer
0/1/2/3
16-bit
PWC timer
8-bit
expanded serial I/O
16-bit
reload timer 0
CPU
External interrupt
USB function
USB HOST
2
I C interface
3
Oscillation stabilization
wait time
CHAPTER 5 CLOCK
5.1 Outline of Clock
Pin
Pin
Pin
Pin
Pin
Pin
UART0/1
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
PPG0 to PPG3
PWC
SCK
SIN
SOT
SCK0, SCK1
SIN0, SIN1
SOT0, SOT1
TIN0
TOT0
INT0 to INT7
DVP
DVM
HCON
UTEST
HVP
HVM
SCL0
SDA0
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