Fujitsu MB90335 Series Hardware Manual page 276

MB90335 Series
[bit 4] URIRQ: USB bus interrupt request
It is shown that reset in USB bus ended. When it becomes "1", it gets back to "0" by writing "0" to it.
When you write "1" to it, the current state will be preserved. If the URIRE bit in the host control
register 0 (HCNT0) is "1", an interrupt is generated when it is "1". The interrupt signal is cleared when
it is cleared with "0".
To update them, you must set the RST bit in the UDC control register (UDCC) to "0".
[bit 3] CMPIRQ: Completion interrupt request
It is shown to have completed the token. It is not set to "1" when the TCAN bit in the host interrupt
register (HIRQ) is "1". When it becomes "1", it gets back to "0" by writing "0" to it. When you write
"1" to it, the current state will be preserved. If the CMPIRE bit in the host control register 0 (HCNT0) is
"1", an interrupt is generated when it is "1". The interrupt signal is cleared when it is cleared with "0".
To update them, you must set the RST bit in the UDC control register (UDCC) to "0".
[bit 2] CNNIRQ: Connected interrupt request
It is shown to have detected the connection of the device. When it becomes "1", it gets back to "0" by
writing "0" to it. When you write "1" to it, the current state will be preserved. If the CNNIRE bit in the
host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1". The interrupt signal is
cleared when it is cleared with "0".
It is not initialized with the RST bit in the UDC control register (UDCC).
CM44-10137-6E
URIRQ
0 There is no interrupt request by USB bus reset.
1 There is an interrupt request by USB bus reset.
CMPIRQ
0 There is no interrupt request by token completion.
1 There is an interrupt request by the token completion.
CNNIRQ
0 Interrupt request none by device connection detection.
1 Indicates interrupt request due to device connection detected.
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 12 USB HOST
12.4 Register of USB HOST
Operation mode
Operation mode
Operation mode
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